Advanced Micro Devices Corporation

Ati Technologies Ulc

Samsung Electronics Co., Ltd.

Saurabh Sharma

Hashem Hashemi

Laurent Lefebvre

Ruijin Wu

Guennadi Riguer

Sagar Shankar Bhandare

Gianpaolo Tommasi

Jeremy Lukacs

Christopher Jude Brennan

Mika Tuomi

Matthew J Fritz

Mehmet Yunt

Paavo Pessi

Venkata Pakkala

Santosh Chikoti

Priyadarshi Sharma

Anshuman Mittal

A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.

Intermediate cache management for non-uniform memory architecture

A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.

Cache blocking for dispatches

A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of cache lines of the repeating pattern of data from the cache. By restricting the cache to store only a subset of cache lines of the repeating pattern of data, the cache controller increases the hit rate at the cache for the subset of cache lines.

Stochastic optimization of surface cacheability in parallel processing units

Systems, apparatuses, and methods for performing dead surface invalidation are disclosed. An application sends draw call commands to a graphics processing unit (GPU) via a driver, with the draw call commands rendering to surfaces. After it is determined that a given surface will no longer be accessed by subsequent draw calls, the application sends a surface invalidation command for the given surface to a command processor of the GPU. After the command processor receives the surface invalidation command, the command processor waits for a shader engine to send a draw call completion message for a last draw call to access the given surface. Once the command processor receives the draw call completion message, the command processor sends a surface invalidation command to a cache to invalidate cache lines for the given surface to free up space in the cache for other data.

Dead surface invalidation

Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

Compressing texture data on a per-channel basis

The present disclosure includes a prescriptive engine system and a method of using the prescriptive engine system. The method includes receiving information on actions and receiving information on participants, the information on the participants including first suitability information of at least one participant for at least one of the actions, generating, based on the first suitability information, second suitability information for a set of participants for at least one action, allocating, based on the second suitability information, the at least one action to the set of participants, deploying the at least one action to the set of participants, receiving, after the at least one action has been performed, results of the at least one action for each participant in the set of participants, and updating, based on the received results, the first suitability information of each participant in the set of participants for the at least one action.

System and method for a prescriptive engine

Growing community of inventors

Santa Clara, CA, United States of America

Saurabh Sharma