Saankhya Labs Private Limited

Saankhya Labs Pvt. Ltd.

Saurabh Mishra

Subrahmanya Kondageri Shankaraiah

Parag Naik

Gururaj Padaki

Subramanian Krishnan

Anindya Saha

S Harish Krishnan

Santosh Billava

Suman Sanisetty

Gururaj Padki

In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an 'N' point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

Index generation scheme for prime factor algorithm based mixed radix discrete fourier transform (DFT)

A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Digital filter implementation for exploiting statistical properties of signal and coefficients

A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Digital downconversion and fast channel selection of narrowband signals using a wide band RF tuner

A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mharmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mharmonic to obtain a peak position (P), and a carrier frequency offset estimation unit that receives the peak position (P) and estimates the CFO.

Carrier frequency offset estimation scheme, for digital standards with MPSK modulated preamble

A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

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Madhepura, India

Saurabh Mishra