Sandisk Technologies Inc.

Stmicroelectronics International N.v.

International Business Machines Corporation

Cirrus Logic Inc.

Other

Surewaves Mediatech Private Limited

Indusedge Innovations Private Limited

Unilever Plc

Unilever IP Holdings B.v.

Saurabh Kumar Singh

Hemant Shukla

Nitin Bansal

Rajendra Kumar Khare

Abhijit Das

Ravi Ramesh Bhat

Mohammad Mohammad

Mark McCloy-Stevens

Balwant Singh

Anant Kansal

Tushar Vyas

Vikas Minda

Deep Saxena

Sanchit Sanga

Manjit Rath

Prabhvir Sahmey

Bolin Bolin

Cvl Srinivas

Balakuntla Maheshkumar Gurucharan

Rajendra Dwivedi

Aparna Sharma

Raul-Adrian Cernea

Kallol Chatterjee

Sridhar Yadala

Anirudh Amarnath

Terence Orr

Andrew Buist

Simon R Foster

Dave Smith

James Wells

Walter Charles Dietrich, Jr

Rishi Arora

Paulius Cerebiejus

Huy Binh Le

Gurmeet Singh

Regina L Haecker

Robert Hazeu

Gavin Wilson

Niall McGurnaghan

Shivprasanth Shivaprasanth

Apama Sharma

Shivprasanth Shivprasanth

Bm Gurucharan

Prateek Agrawal

Payal Gupta

The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.

Self-test circuitry

The present disclosure relates to current control circuitry for controlling a current through a load. The current control circuitry comprises amplifier circuitry, reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry and an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; and a current output terminal. The current control circuitry further comprises a variable resistance coupled to the current output terminal of the output stage, and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.

Current control circuitry

An oscillator circuit includes a voltage controlled oscillator (VCO) configured to generate a clock signal having a clock period that is adjustable based on a control signal. The oscillator circuit includes a time to voltage converter configured to receive the clock signal and generate a compensation voltage potential that is proportional to the clock period and a zero temperature coefficient (ZTC) current. The oscillator circuit includes an amplifier configured to generate the control signal responsive to the compensation voltage potential and a temperature independent reference voltage potential. A method includes applying a control signal to a VCO, generating a clock signal having a clock period responsive to the control signal, generating a compensation voltage potential, and adjusting the clock period using the compensation voltage potential. A memory device includes the oscillator circuit.

Wide range zero temperature coefficient oscillators and related devices and methods

A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Scheme to measure individually rise and fall delays of non-inverting logic cells

Apparatuses, systems, and methods are disclosed for offset trimming for differential amplifiers. An apparatus includes a differential amplifier. A differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. A first variable current source is coupled to a non-inverting input, so that increasing a current from the first variable current source increases a voltage at the non-inverting input. A second variable current source is coupled to an inverting input, and to an output via a voltage divider, so that increasing a current from the second variable current source decreases a voltage at the output.

Offset trimming for differential amplifier

The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.

Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation

A temperature sensor is disclosed. In one aspect, the temperature sensor provides a digital output having a precise degree/code step. For example, each step in the digital output code may correspond to one degree Celsius. In one aspect, a temperature sensor comprises a precision band-gap circuit and a sigma delta modulator (SDM) analog-to-digital convertor (ADC). A bandgap voltage and a PTAT voltage may be provided from the band-gap circuit as an input to the SDM ADC. The SDM ADC may produce an output based on the difference between the PTAT voltage and the bandgap voltage. The temperature sensor may also have logic that outputs a temperature code based on the output of the SDM ADC.

High accuracy temperature sensor

A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the output. A digital or analog signal is set which turns the discharge transistor on or off. A current pulldown may be arranged in the discharge path.

Voltage regulator with fast overshoot settling response

A sensor that can provide multiple resolutions, based on the output of the same analog-to-digital converter is disclosed. Some applications require a fast measurement of a physical parameter (e.g., temperature, voltage, pressure), but can tolerate a lower resolution measurement. Other applications require a higher resolution measurement, but can tolerate a slower measurement. The sensor may comprise a sigma delta modulator (SDM) ADC that outputs a digital reading. The output may comprise a bus having a width that is equal to the desired highest resolution of the digital code for the physical parameter. The sensor may further comprise a storage unit for each desired level of resolution. The sensor may further comprise logic that causes the storage units to sample the output bus after a certain number of clock cycles in order to store a digital code having a number of bits equal to the resolution.

Multiple resolution temperature sensor

An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.

Circuit for regulating startup and operation voltage of an electronic device

A method and apparatus are provided. The apparatus includes a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.

Voltage regulator

An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.

Capless on chip voltage regulator using adaptive bulk bias

System and method for creating networked short range zone through remote delivery of short range proxy server on a remotely located machine, the method comprising the steps of registering with the system network, receiving a unique ID, accessing the server for further processing, downloading the relevant application with enabling means, connecting a device to short range dongles, running the application and registering the device using the unique ID, entering the location based and/or other relevant information, enabling the device for creating networked short range zone.

System and method for creating networked short range zone through remote delivery of short range proxy server on a remotely located machine

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Bengaluru, India

Saurabh Kumar Singh