Applied Materials, Inc.

Saurabh Chopra

Zhiyuan Ye

Yihwan Kim

Xuebin Li

Yi-Chiau Huang

Christopher Sean Olsen

Lara Hawrylchak

Abhishek Dube

Patricia M Liu

Jeffrey A Tobin

Theresa Kramer Guarini

Peter Stone

Chi Wei Lo

Gaurav Thareja

Shu-Kwan Danny Lau

Martin Jeffrey Salinas

Sanjay S Natarajan

Ala Moradian

Andrew C Lam

Zuoming Zhu

Chia Cheng Chin

Andy Lo

Chen-Ying Wu

Er-Xuan Ping

Schubert S Chu

Errol Antonio C Sanchez

John Tolle

Zhepeng Cong

Thomas Jongwan Kwon

Masato Ishii

Tushar Mandrekar

Flora Fong-Song Chang

Jenny Lin

Vilen K Nestorov

Enle Choo

Bindusagar Marath Sankarathodi

Manjunath Subbanna

Sathya Chary

Surendra Singh Srivastava

Srividya Natarajan

Thomas Kirschenheiter

Maxim Shaposhnikov

Sungwon Jun

Sheng-Chen Twan

The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.

Flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability

An apparatus for controlling temperature profile of a substrate within an epitaxial chamber includes a bottom center pyrometer and a bottom outer pyrometer to respectively measure temperatures at a center location and an outer location of a first surface of a susceptor of an epitaxy chamber, a top center pyrometer and a top outer pyrometer to respectively measure temperatures at a center location and an outer location of a substrate disposed on a second surface of the susceptor opposite the first surface, a first controller to receive signals, from the bottom center pyrometer and the bottom outer pyrometer, and output a feedback signal to a first heating lamp module that heats the first surface based on the measured temperatures of the first surface, and a second controller to receive signals, from the top center pyrometer, the top outer pyrometer, the bottom center pyrometer, and the bottom outer pyrometer, and output a feedback signal to a second heating lamp module that heats the substrate based on the measured temperatures of a substrate and the measured temperatures of the first surface.

Temperature profile measurement and synchronized control on substrate and susceptor in an epitaxy chamber

Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

Anisotropic sige:b epitaxial film growth for gate all around transistor

In one aspect, a process operation is conducted at a first pressure in a process chamber, and an epitaxial deposition operation is conducted at an atmospheric pressure in an epitaxial deposition chamber. The atmospheric pressure is greater than the first pressure. The process chamber is mounted to a first mainframe that operates at the first pressure (a reduced pressure), and the epitaxial deposition chamber is mounted to a second mainframe that operates at the atmospheric chamber. In one aspect, the process chamber is a cleaning chamber (such as a pre-clean chamber) and the process operation is a cleaning operation. In one aspect, the process chamber is an atmospheric pressure epitaxial deposition chamber and the process operation is an atmospheric pressure epitaxial deposition operation.

Cluster tools, systems, and methods having one or more pressure stabilization chambers

One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

Selective methods for fabricating devices and structures

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Method of fabricating a semiconductor device having reduced contact resistance

The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Semiconductor device, method of making a semiconductor device, and processing system

Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.

Method and apparatus for precleaning a substrate surface prior to epitaxial growth

A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560&#xb0; C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.

Self-aligned nanodots for 3D NAND flash memory

Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1&#xd7;10atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1&#xd7;10atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.

Epitaxy of high tensile silicon alloy for tensile strain applications

Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters.

Carbon addition for low resistivity in situ doped silicon epitaxy

Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH).

Methods of selectively depositing an epitaxial layer

Growing community of inventors

Santa Clara, CA, United States of America

Saurabh Chopra