Apple Inc.

Altera Corporation

Synopsys, Inc.

Intel Corporation

Saurabh Adya

Mahesh A Iyer

Alkeshkumar M Patel

Love Singhal

Myra C Lukens

Kenneth S McElvain

Gael Paul

Srikanth Vishnubhotla

Ahmed S Hussen Abdelaziz

Herman Henry Schmit

Dana How

Aswath Manoharan

Sachin S Kajarekar

Carl Ebeling

Chaitanya Mannemala

Barry-John Theobald

Lin Li

Xiaochuan Niu

Nikolay Rubanov

Karan M Daryanani

Sameer Badaskar

Pranay Dighe

Seyedmahdad Mirsamadi

Ognjen Rudovic

Shounak Dhar

Hong Yu

Jianpeng Cheng

Shruti Bhargava

Stephen G Pulman

Dhivya Piraviperumal

Akanksha Bindal

Ahmed H Tewfik

Erik Marchi

Alexander W Churchill

Systems and processes for operating a digital assistant are provided. An example process for determining a response includes, at an electronic device having one or more processors and memory, receiving a spoken input including a request, performing a semantic analysis on the spoken input, determining, based on the semantic analysis, a likelihood that the electronic device requires additional contextual data to satisfy the request, and in accordance with the determined likelihood exceeding a threshold, enabling a camera of the electronic device and determining a response to the request based on data captured by the camera of the electronic device.

Selectively using sensors for contextual data

Systems and processes for operating an intelligent automated assistant are provided. An example process includes receiving an utterance including a user request and determining whether at least a portion of the user request is ambiguous. If at least the portion of the user request is ambiguous then a set of context data based on the ambiguous portion of the user request is determined, metadata is extracted from the context data and a response to the user request is determined based on the extracted metadata.

Multimodal assistant understanding using on-screen and device context

An example process includes: receiving a speech input representing a user utterance; determining, based on a textual representation of the speech input, a first score corresponding to a type of the user utterance; determining, based on the textual representation of the speech input, a second score representing a correspondence between the user utterance and a domain recognized by a digital assistant; determining, based on the first score and the second score, whether the speech input is intended for the digital assistant; in accordance with a determination that the speech input is intended for the digital assistant: initiating, by the digital assistant, a task based on the speech input; and providing an output indicative of the initiated task.

Determining whether speech input is intended for a digital assistant

Systems and processes for operating a digital assistant are provided. An example method for processing an image include receiving an image, generating, based on the image, a question corresponding to a first object in the image, generating, based on the image, a caption corresponding to a second object of the image, receiving an utterance from a user, and determining a plurality of speech recognition results from the utterance based on the question and the caption.

Using visual context to improve a virtual assistant

Systems and processes for operating a digital assistant are provided. An example process for performing a task includes, at an electronic device having one or more processors and memory, receiving a spoken input including a request, receiving an image input including a plurality of objects, selecting a reference resolution module of a plurality of reference resolution modules based on the request and the image input, determining, with the selected reference resolution module, whether the request references a first object of the plurality of objects based on at least the spoken input, and in accordance with a determination that the request references the first object of the plurality of objects, determining a response to the request including information about the first object.

Digital assistant reference resolution

Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed.

Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph

A method for designing a system on a target device includes placing the system on the target device. A netlist retiming is performed on the placed system. A clock allocation and a clock region optimization are performed utilizing information from the placing and the netlist retiming.

Method and apparatus for performing clock allocation for a system implemented on a programmable device

Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

Methods for minimizing logic overlap on integrated circuits

A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.

Method and apparatus for performing large scale consensus based clustering

A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

Sector-based clock routing methods and apparatus

In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.

Methods and apparatuses for circuit design and optimization

In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion.

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San Jose, CA, United States of America

Saurabh Adya