Sandisk Corporation

Samsung Electronics Co., Ltd.

Multi Level Memory Technology

Invox Technology

Invoice Technology, Inc.

Other

Sau Ching Wong

Hock C So

Cheng-Yuan Michael Wang

Carl William Werner

Leon Sea Jiunn Wong

Andreas M Haeberli

Leo Petropoulos

Frank M Dunlap

Masahiko Watanabe

Tsuyoshi Ono

John H Chan

Kimberley Johnsen

Roger Ying Kuen Lo

Yasuaki Hirano

Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

Programming nonvolatile memory cells through a series of predetermined threshold voltages

Adaptive parallel writing to nonvolatile memory cells

Programming nonvolatile memory cells using resolution-based and level-based voltage increments

Parallel programming of nonvolatile memory cells

Reading a multi-bit value from a memory cell

Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.

Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage

Adaptive operations for nonvolatile memories

Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells () capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency

A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process checks whether a threshold voltage is in a forbidden zone. Alternately, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be performed in response to detecting a threshold voltage in a forbidden zone or periodically.

Multi-bit-per-cell flash EEPROM memory with refresh

A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Fabricating bi-directional nonvolatile memory cells

Growing community of inventors

Hillsborough, CA, United States of America

Sau Ching Wong