Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Vsli Technology, Inc.

Philip Semiconductors, Inc.

Satyendra S Sethi

Daniel C Baker

Kouros Ghandehari

Dipankar Pramanik

Calvin T Gabriel

Subhas Bothra

Jacob D Haskell

Ian Robert Harvey

Xi-Wei Lin

Milind Ganesh Weling

Henry C Lee

Sudhir G Subramanya

Clifford Takemoto

A method for inspecting features on a reticle is provided. The method includes providing a layout design of a test feature and transferring the layout design of the test feature onto the reticle. After the test feature is transferred onto the reticle, an image of the transferred layout design is captured to determine whether or not the transfer is acceptable. This determination is made by comparing the captured image of the transferred layout design against the layout design of the test feature. The comparison ascertains deviations between the captured image and the layout design and determines if the deviations fall within a user specified range.

Methods for the automated testing of reticle feature geometries

In one example embodiment, a method of forming a pattern in a photoresist material includes illuminating a portion of the photoresist material according to the pattern and positioning a filter in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.

Method of illumination uniformity in photolithographic systems

A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reduction lens is placed between the mask and the wafer in order to direct and expose the mask's features onto the wafer. Furthermore, a reflective member is disposed proximate to the reduction lens. In order to achieve finer resolution of the mask image on the wafer, this reflective member captures diffracted light diffracting beyond the reduction lens and redirects the diffracted light to pass through the reduction lens such that the diffracted light is redirected onto the wafer. In so doing, the reflective member resolves the mask image on the wafer in more detail than is possible by an optical lithography process using no such reflective member.

Modified optics for imaging of lens limited subresolution features

A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

Use of optimized film stacks for increasing absorption for laser repair of fuse links

The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed. According to exemplary embodiments, the wavelength of the energy source selected, such as an infrared light source, can be determined on the basis of an absorption coefficient of the planarized opaque material through which edge detection is to be performed (e.g., through a planarized polysilicon layer), and on the basis of a predetermined thickness with which the planarized polysilicon layer is formed.

Method and apparatus for detecting edges under an opaque layer

The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.

Sacrificial multilayer anti-reflective coating for mos gate formation

An apparatus for forming a pattern in a photoresist material includes a light source to provide light for illuminating a portion of the photoresist material according to the pattern and a filter positioned in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.

Apparatus and method for the improvement of illumination uniformity in photolithographic systems

A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Via alignment, etch completion, and critical dimension measurement method and structure

Via alignment, etch completion, and critical dimension measurement

A method and apparatus for the alignment of a semiconductor device in preparation for patterning a layer of the device includes using an alignment apparatus which has one or more light sources for producing light at two or more alignment wavelengths. Typically, the semiconductor device will include alignment structures that are to be aligned with corresponding alignment markers on a photomask which contains the desired pattern. The alignment structures on the semiconductor device are often depressions or trenches in a layer of the device. The alignment apparatus determines the position of the alignment structures by observing the contrast in the intensity of light reflected off the region of the device containing the alignment structure and the region of the device adjacent to the alignment structure. This contrast in the intensity of light is wavelength dependent. By providing an alignment apparatus with multiple alignment wavelengths, it is likely that at least one of those wavelengths will provide sufficient contrast to accurately resolve the alignment structures.

Method for alignment using multiple wavelengths of light

A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating. The portions of the antireflective coating, the sacrificial layer, and the semiconductor substrate which are not covered by the patterned layer of photoresist material are then removed to define features of an IC. After the patterning of IC features, the sacrificial layer is removed from the IC features to lift the antireflective coating off such features. IC devices formed in accordance with these methods also are provided.

Method of removing an inorganic antireflective coating from a

A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.

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Pleasanton, CA, United States of America

Satyendra S Sethi