Texas Instruments Corporation

Satyavolu Srinivas Papa Rao

Stephan Grunow

Phillip D Matz

Kenneth D Brennan

Timothy Alan Rost

Noel M Russell

Edmund David Burke

Sameer Kumar Ajmera

Byron Lovell Williams

Kelly Jay Taylor

Robert Kraft

Ting Yiu Tsui

Darius Lammont Crenshaw

Montray Leavy

Sanjeev Aggarwal

Haowen Bu

Asad Mahmood Haider

Rose Alyssa Keagy

Ed Burke

Richard L Guldi

Lindsey H Hall

Alwin J Tsao

Hisashi Shichijo

Michael Francis Pas

Stephanie Watts Butler

Cloves Rinn Cleavelin

Duofeng Yue

Andrew McKerrow

Basab Chatterjee

Steven Alan Lytle

Somit Joshi

Edward Raymond Engbrecht

Valli Arunachalam

Zhibo Zhang

Mike Watson Goodwin

Yuri E Solomentsev

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection cladding () for the copper metal () of the top metal interconnect.

Capacitor integration at top-metal level with a protective cladding for copper surface protection

In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Properties of metallic copper diffusion barriers through silicon surface treatments

An inductor structure () formed in an integrated circuit () is disclosed, and includes a first isolation layer () and a first core plate () disposed over or within the first isolation layer (). The first core plate () includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer () overlies the first isolation layer and an inductor coil () composed of a conductive material layer () is formed within the second isolation layer (). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil ().

Method to improve inductance with a high-permeability slotted plate core in an integrated circuit

The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (). A strain inducing liner is formed over the semiconductor device (). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region ().

Systems and methods that selectively modify liner induced stress

The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Method of fabrication of on-chip heat pipes and ancillary heat transfer components

The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Energy beam treatment to improve packaging reliability

Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than &#x3c;1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.

Manufacturable reliable diffusion-barrier

A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Air gap in integrated circuit inductor fabrication

In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Methods and devices employing metal layers in gates to introduce channel strain

An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuithaving a back-end structurecoupled to a front-end structure. The back-end structurehaving a first metal level. The first metal levelhaving metal interconnectsand an inter-metal dielectric layer. The back-end structurefurther containing an extraction lineand a denuded dielectric regioncoupled to the extraction line

Use of supercritical fluid for low effective dielectric constant metallization

An integrated circuit capacitor having a bottom plate, a dielectric layer', and a ferromagnetic top plate.

Ferromagnetic capacitor

Growing community of inventors

Garland, TX, United States of America

Satyavolu Srinivas Papa Rao