Texas Instruments Corporation

Satyavolu Papa Rao

Basab Chatterjee

Richard L Guldi

Vincent C Korthuis

Mona M Eissa

Tae S Kim

Changming Jin

Sopa Chevacharoenkul

Ju-Ai Ruan

Barry Lanier

Chad J Kaneshige

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Semiconductor device manufactured by reducing hillock formation in metal interconnects

A system ( ) for detecting defects in a semiconductor wafer ( ), such defects including voids (V) present in metal conductors ( ) and plugs ( ), is disclosed. An x-ray source ( ) irradiates the wafer ( ) through a first aperture array ( ) having openings ( ); a second aperture array ( ) is located on the opposite side of the wafer ( ) from the source ( ), and has openings ( ) that are aligned and registered with the openings ( ) in the first aperture array ( ). An array of x-ray detectors ( ) is located adjacent to the second aperture array ( ), with each detector ( ) associated with one of the openings ( ) of the second aperture array ( ). The detectors ( ) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer ( ) at locations defined by the openings ( ) through aperture arrays ( ), to an analysis computer ( ). A wafer translation system ( ) indexes or otherwise moves the wafer ( ) between the aperture arrays ( ). The analysis computer ( ) generates an x-ray image of the wafer ( ) from the detected x-ray energy, or alternatively compares the detected x-ray energy at locations of wafer ( ) to automatically detect and distinguish defects.

X-ray defect detection in integrated circuit metallization

A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer. The process also includes the steps of simultaneously buffing a second wafer with the buffing pad for a second length of time, in which the first length of time is greater than the second length of time, and rinsing the buffing pad and the buffed wafer with a moisture maintenance compound for at least a portion of the time between the completion of the second length of time and the first length of time. Moreover, the moisture maintenance compound substantially prevents drying of the buffed wafer between the completion of the second length of time and the first length of time.

Processes for chemical-mechanical polishing of a semiconductor wafer

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Garland, TX, United States of America

Satyavolu Papa Rao