Globalfoundries U.S. Inc.

International Business Machines Corporation

Satyasuresh V Choppalli

Anupam Dutta

Robert J Gauthier, Jr

Rajendran Krishnasamy

Josef S Watts

Anindya Nath

Prabhu R Dattatreya

John J Ellis-Monaghan

Michel J Abou-Khalil

Venkata N R Vanukuru

Lin Lin

Xiangxiang Lu

Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

Gate tunnel current-triggered semiconductor controlled rectifier

Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

Integrated circuit structure with resistive semiconductor material for back well

Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Integrated circuit (IC) structure with high impedance semiconductor material between substrate and transistor

Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.

Methods of manufacturing polyresistors with selected TCR

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Bengaluru, India

Satyasuresh V Choppalli