Arm Limited

Satyanand Vijay Nalam

Robert Campbell Aitken

Vikas Chandra

Cezary Pietrzyk

A static random access memory (SRAM) includes a data line for transferring data to and from the memory and at least one reset line, a plurality of storage cells, each cell including an asymmetric feedback loop; an access device for selectively providing a connection between the at data line and the cell's first access node; a reset device for selectively providing a connection between a reset line and the cell's second access node. The SRAM further includes data access control circuitry for generating control signals for independently controlling the access device and the reset device and to generate a data access control signal. The SRAM also generates a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.

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Charlottesville, VA, United States of America

Satyanand Vijay Nalam