Xilinx, Inc.

Satyaki Das

Christopher H Kingsley

Arifur Rahman

Tim Tuan

Jason Helge Anderson

Sandor S Kalman

Vinay Verma

Sanjeev Kwatra

Taneem Ahmed

Yu Hu

Stephen M Trimberger

Austin H Lesea

Anirban Rahut

Sean W Kao

Gitu Jain

Jitu Jain

Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.

Multi-threaded deterministic router

A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product

A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile templates are associated with tiles of an integrated circuit. The tiles are repeated circuit blocks forming an array. A portion of the tile templates are shared among a portion of the tiles such that the tile templates are less in number than the tiles. The tile templates are associated with pointers for pointing to wire templates.

Multilevel shared database for routing

A method of determining validity of slice packing for a programmable device can include identifying a slice topology for a slice, identifying a circuit fragment assigned to the slice, and generating a set of Boolean equations describing conditions for mapping the circuit fragment to the slice according to the slice topology. The method further can include determining whether a solution to the set of Boolean equations exists and indicating whether the slice is validly packed according to whether a solution for the set of Boolean equations is determined.

Checking for valid slice packing in a programmable device

A computer-implemented method of balancing logic resource usage in a circuit design for a programmable integrated circuit (IC) includes determining that an assignment of elements of the circuit design to a first type of logic resource is unbalanced compared to an assignment of elements to an alternate type of logic resource. Binary variables are defined for circuit elements assigned to the first and alternate types of logic resources, where each binary variable indicates whether the associated circuit element is to be re-assigned to the first or alternate type of logic resource. Constraints are defined specifying relationships among selected variables. Values for the variables are obtained according to the constraints by minimizing a function dependent on a sum of the binary variables. Circuit elements are re-assigned to the first or alternate types of logic resources according to the values determined for the binary variables, and the circuit design is output.

Methods of balancing logic resource usage in a programmable logic device

A computer-implemented method of balancing logic resource usage in a circuit design for a programmable logic device (PLD) can include determining that an assignment of elements of the circuit design to a first type of logic resource of the PLD is unbalanced compared to an assignment of elements of the circuit design to an alternate type of logic resource of the PLD. An Integer Linear Programming (ILP) formulation specifying a balanced assignment of elements to the first and alternate types of logic resources can be generated. A solution for the ILP formulation can be obtained. Selected elements of the circuit design can be re-mapped from the first type of logic resource to the alternate type of logic resource according to the solution of the ILP formulation and the circuit design specifying the re-mapped elements can be output.

Balancing logic resource usage in a programmable integrated circuit

A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

Structures and methods for heterogeneous low power programmable logic device

Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

Growing community of inventors

San Jose, CA, United States of America

Satyaki Das