Redpine Signals, Inc.

Satya Rao

Narasimhan Venkatesh

Partha Sarathy Murali

Heonchul Park

Dharani Naga Sailaja Sankabathula

Chandra Sekhar Ponnamanda Venkata

A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data stream, a digital signal processor for converting the stream of multiplexed data into a media access controller format, and a media access controller for demultiplexing and framing the stream of data into a plurality of data buffers, one data buffer for each wireless session.

Multi-thread media access controller with per-thread MAC address

A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H', thereafter generating Q&#x2032; and R&#x2032; subject to the same constraints as was described for Q and R. Transformed variables Z and Z&#x2032; are formed by multiplying Y by Qand Q&#x2032;, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of xderived from xand Z, and also including a distance metric. The reduced complexity maximum likelihood decoder has a second part which accepts Z&#x2032; and R&#x2032; and forms a second metric table having entries of all possible xaccompanied by estimates of xderived from xand Z&#x2032;, and also including a distance metric. A hard decision is made by finding the minimum distance metric of the combined entries of the first and second table. Soft values are also computed using this table.

Packet buffer management apparatus and method

During the preamble interval of a wireless packet, a receiver estimates the SINR of the preamble, and also examines the packet header to determine the data rate, length, and destination address. If the SINR as determined from the preamble is below a threshold, or if the SINR combined with the data rate from the packet header is below a threshold, the receiver is powered down for the duration of the current packet. Additionally, if the packet header bears a destination address for a different station from the one receiving it, the receiver is powered down for the duration of the packet. In this manner, the receiver power is only used to receive packets that have sufficient SINR to be correctly received for their data rate, or are destined for the present station. The reduction in power consumption results in longer battery life for the station.

SINR-based powerdown apparatus and method for a wireless communications systems

A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to 'used' or 'free', and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data. Data is removed from packet memory based on which queue the data may be found in. The queues are based on a priority system, where one queue receives priority over another queue for data reception and transmission.

An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.

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Hyderabad Telangana, India

Satya Rao