Nvidia Corporation

Satya Puvvada

Amit D Sanghani

Milind Bhaiyyasaheb Sonawane

Anubhav Sinha

Vishal Agarwal

A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.

System for reducing peak power during scan shift at the local level for scan based tests

A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

System for reducing peak power during scan shift at the global level for scan based tests

A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

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San Jose, CA, United States of America

Satya Puvvada