International Business Machines Corporation

Satya Prakash Sharma

Ravi Kumar Arimilli

Randal Craig Swanberg

Balaram Sinharoy

Bruce Gerard Mealey

Peter H Hochschild

Rama Krishna Govindaraju

Andrew Dunshea

Diane Garza Flemming

Mysore Sathyanaranyana Srinivas

William A Maron

Ravi Shankar

David Alan Hepkin

Mysore Sathyanarayana Srinivas

James P Allen

Rakesh Sharma

Thomas Stanley Mathews

Ram Raghavan

Glenn Rowan Wightwick

Saurabh Nath Sharma

Claude Basso

Fabrice Jean Verplanken

Jean Louis Calvignac

Colin Beaton Verrilli

Vinit Jain

Natarajan Vaidhyanathan

Balakrishna Raghavendra Iyer

Chih-Jen Chang

Philippe Damon

Ronald Edward Fuhs

Inderpal Singh Narang

Casper A Scalzi

Scott Michael Willenborg

Richard I Baum

Glen A Brent

Bhaskar Sinha

Lee Hardy Wilson

Frank Dea

Gururaj Seshagiri Rao

Helmut Cossmann

Hatem Mohamed Ghafir

William James Hymas

Gururaj S Rao

Herman Dierks

Randall Craig Swanberg

Hatem M Ghafir

Lee H Wilson

A system, and computer usable program product for expanding memory size are provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory.

Expanding memory size

A data processing system comprises at least one processing unit, a virtualization layer, and a remote update programming idiom accelerator. The remote update programming idiom accelerator is configured to receive a complex remote update programming idiom from a remote node. Responsive to a determination that the sequence of instructions in the complex remote update programming idiom is longer than a dedicated processor threshold, the remote update programming idiom accelerator is configured to request a processing unit from the virtualization layer in the data processing system, and receive an allocation of a processing unit from the virtualization layer. The allocated processing unit is configured to read the data from the storage location local to the data processing system, execute the sequence of instructions to perform the update operation on the data to form result data, and write the result data to the storage location local to the data processing system.

Remote update programming idiom accelerator with allocated processor resources

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is spinning on a lock. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the lock and sets a lock bit in the wake-and-go array. The thread then goes to sleep until the lock frees. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the thread that is spinning on the lock.

CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock

A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an action to accelerate execution of the programming idiom. In the case of a wake-and-go programming idiom, the programming idiom accelerator may record an entry in a wake-and-go array, for example.

Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors

A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an action to accelerate execution of the programming idiom. A compiler may recognize programming idioms and expose the programming idioms to the programming idiom accelerator within the resulting machine language instructions.

Compiler providing idiom to idiom accelerator

A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the programming idiom accelerator. Thus, the programming idiom accelerator need not perform pattern matching or other forms of analysis to recognize a sequence of instructions. Rather, the programmer may insert idiom hint instructions, such as an idiom begin hint, to expose the idiom to the programming idiom accelerator. Similarly, an idiom end hint may mark the end of the programming idiom.

Programming language exposing idiom calls to a programming idiom accelerator

Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

Mixed operating performance modes including a shared cache mode

A wake-and-go mechanism is provided for a data processing system. When a thread first starts executing, a wake-and-go mechanism automatically allocates space for thread state in a hardware private array and space for a target address and other information, if any, in a wake-and-go array. If the hardware private array comprises a reserved portion of system memory, then the wake-and-go mechanism may request a sufficient portion of memory to store thread state for the thread. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. When a thread ends execution and is no longer in the run queue of the processor, the wake-and-go mechanism de-allocates the space for the thread state information for that thread.

Wake-and-go mechanism with dynamic allocation in hardware private array

A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.

Wake-and-go mechanism with hardware private array

A mechanism is provided for communicating between a plurality of applications. An application programming interface (API) associated with an originating application running on a first logical partition in a plurality of logical partitions of a logically partitioned data processing system receives a request to send data to a destination application. The API sends a request to identify a location of the destination application to a virtualization management mechanism. Responsive to receiving a response from the virtualization management mechanism, the API determines whether the location of the destination application is in a second logical partition in the plurality of logical partitions of the logically partitioned data processing system. Responsive to the location being in the second logical partition, the API uses a bypass protocol to send the request from the originating application to the destination application.

High performance and resource efficient communications between partitions in a logically partitioned system

A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. Software may save the state of the thread. The thread is then put to sleep. When the wake-and-go array snoops a kill at a given target address, logic associated with wake-and-go array may generate an exception, which may result in a switch to kernel mode, wherein the operating system performs some action before returning control to the originating process. In this case, the trap results in other software, such as the operating system or background sleeper thread, for example, to reload thread from thread state storage and to continue processing of the active threads on the processor.

Wake-and-go mechanism with software save of thread state

A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Wake-and-go mechanism for a data processing system

A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the one or more threads waiting for the event.

Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms

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Austin, TX, United States of America

Satya Prakash Sharma