Intel Corporation

University of Minnesota

Satwik Patnaik

Ashoke Ravi

Benjamin Jann

Sachin Kalia

Ramesh Harjani

Bodhisatwa Sadhu

Martin D Sturm

Ofir Degani

Alexandros Margomenos

Elan Banin

Igal Kushnir

Hyung-Jin Lee

Mohammad Elbadry

Ram Sadhwani

Sanket Jain

A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.

Methods and devices for selecting a desired sub-harmonic of a high-frequency clock

Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Local oscillator (LO) generation for carrier aggregation in phased array front ends

Injection-locked clock-multiplication for mixer local oscillator (LO) generation

Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.

Radio design, control, and architecture

Digital radio head control

A voltage controlled oscillator (VCO) circuit is disclosed. The VCO circuit comprises a VCO tuning circuit comprising a primary inductive coil. In some embodiments, the VCO tuning circuit is configured to generate a VCO output signal at a first resonance frequency. The VCO circuit further comprises a filter circuit comprising a secondary inductive coil. In some embodiments, the filter circuit is configured to resonate at a second, different, resonance frequency, in order to filter a noise associated with the VCO tuning circuit. In some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are concentrically arranged with respect to one another. Further, in some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are magnetically decoupled with respect to one another.

Magnetically decoupled concentric coils structure for area optimized high performance LC VCOs

A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.

Pseudo true time delay for multi-antenna systems

Multi-stage charge re-use analog circuits

Growing community of inventors

Portland, OR, United States of America

Satwik Patnaik