Brocade Communications Systems, Inc.

Vexata, Inc.

Ampere Computing LLC

Satsheel Altekar

Kung-Ling Ko

Surya Prakash Varanasi

John Michael Terry

Venkatesh Nagapudi

Venkata Pramod Balakavi

Zahid S Hussain

Surya Parkash Varanasi

Ramkumar Vadivelu

Vinodh Ravindran

Shailendra Jha

Vikram Bichal

Sridhar Kotha

Satyanarayana Arvapalli

Anil Kumar Gajkela

Srinivas Reddy Bhima Reddy

Balajl Tadepalli

Vankata Pramod Balakavi

Venkatesh Nagapudl

An improved storage replication scheme removes the bottlenecks in the data replication path and allows for high performance replication, both synchronous and asynchronous. The scheme eliminates storage array controllers from the replication data path and provides an implementation of array based replication which can sustain much higher input/output (I/O) write bandwidth with much lower latency from the application's perspective.

High performance and low-latency replication using storage mirroring

Various embodiments provide for a system that integrates 64 bit ARM cores and a switch on a single chip. The RISC style processors use highly optimized sets of instructions rather than the specialized set of instructions found in other architectures (e.g., x86). The system also includes multiple high bandwidth ports that enable multi-ported virtual appliances to be built using a single chip. The virtual appliances are software implemented versions of the physical appliances that are installed with servers to provide network services such routing and switching services, firewall, VPN, SSL, and other security services, as well as load balancing. The virtual appliances are implemented in software and the system can add new virtual appliances, or change the functions performed by existing virtual appliances flexibly without having to install or remove physical hardware.

Virtual appliance on a chip

Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Storage architecture for storage class memories

A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.

Dynamic latency-based rerouting

Apparatuses and methods to mirror frames received at an input port or provided by an output port to a port not connected to the device performing the mirroring operation. A frame being sent to a diagnostic system has a mirror header added to allow the frame to be routed through any intervening switches in the same fabric. The final switch or the diagnostic system removes the mirror header. If the diagnostic system is attached in a different fabric, encapsulation and inter-fabric routing headers are added as needed to the frame containing the mirror header. This allows the frame to traverse multiple fabrics to reach the diagnostic system. The encapsulation and inter-fabric routing headers are removed as done normally. This allows a diagnostic system to be connected to any switch in the network, either in the same or a different fabric.

Method and apparatus for mirroring frames to a remote diagnostic system

Longest Prefix Match (LPM) is implemented using a binary tree based search algorithm. Masked entries are stored in a plurality of binary search engines, wherein each of the binary search engines stores masked entries of a corresponding mask length. A search value is applied to each of the binary search engines in parallel. The search value is masked within each of the binary search engines, thereby creating a plurality of masked search values, each having a masked length equal to the mask length of the corresponding binary search engine. Each of the masked search values is compared with the masked entries of the corresponding binary search engine. An LPM result is selected from the binary search engine that detects a match, and has the longest corresponding mask length. Alternately, each binary search engine stores masked entries of N mask lengths, and N consecutive comparisons are performed to identify the LPM.

Longest prefix match using binary search tree

Growing community of inventors

San Jose, CA, United States of America

Satsheel Altekar