Kabushiki Kaisha Toshiba

Satoshi Yamano

Shigeo Ohshima

Jumpei Sato

Masakazu Kiryu

Tsuyoshi Etou

Souichi Minemura

Osamu Ooto

According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Semiconductor memory device, method for designing semiconductor memory device, and recording medium having designing method recorded therein

A FIFO memory device using a serial pointer consists of first and second memory cell arrays, a row decoder for selecting a word line, first and second write registers for storing data, each write register consisting of registers, and a serial write pointer for serially selecting each register. The serial write pointer consists of pointers corresponding to the first and second write registers. The row decoder is located between the first memory cell array and the second memory cell array. In the device, in adjacent registers in each write register, the shift direction of one register indicated by said serial write pointer is opposed to the shift direction of the other register.

Semiconductor memory device using serial pointer

A FIFO memory device using a serial pointer consists of first second memory cell arrays, a row decoder for selecting a word line first and second write registers for storing data, each write register consisting of registers, and a serial write pointer for serially selecting each register. The serial write pointer consists of pointers corresponding to the first and second write registers. The row decoder is located between the first memory cell array and the second memory cell array. In the device, in adjacent registers in each write register, the shift direction of one register indicated by said serial write pointer is opposed to the shift direction of the other register.

A semiconductor device is provided with a first protection path between a first terminal and an input terminal, a second protection path between a second power source terminal and the input terminal, and a third protection path between the first and the second power source terminals. Each protection path includes a first and a second P-N junction formed to be reverse biased, and is made conductive when the voltage between the corresponding two terminals exceeds a predetermined voltage so as to protect an internal circuit connected to the input terminal from an electrostatic breakdown.

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Kawasaki, Japan

Satoshi Yamano