Hitachi, Ltd.

Solid State Storage Solutions LLC

Renesas Technology Corp.

Satoshi Watatani

Kiyoshi Inoue

Kunihiro Katayama

Shigemasa Shiota

Takayuki Tamura

Masashi Naito

A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Semiconductor memory device having faulty cells

In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Nonvolatile memory with faulty cell registration

Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory

A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

Growing community of inventors

Yokohama, Japan

Satoshi Watatani