Hitachi, Ltd.

Satoshi Ueno

Takashi Harada

Hiroshi Kikuchi

Norio Nakazato

Shinya Kajiyama

Shinichiro Wada

Fujiaki Nose

Kiyoshi Hayashi

Nobuhiro Shiramizu

Keiki Watanabe

Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.

Semiconductor device and a method of manufacturing the same

In a circuit for converting an input signal Dataof high frequency to an output signal Dataof low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a transmitting circuit capable of converting first parallel signals to a first serial signal, a receiving circuit capable of converting a second serial signal to second parallel signals, a test signal generating circuit, and an operation judging circuit, all of which are formed on a single semiconductor chip. The test signal generating circuit and the operation judging circuit are formed so as to operate in accordance with a clock having a frequency corresponding to a transfer rate of the first or second parallel signals.

Semiconductor integrated circuit having a self-testing function

In a circuit for converting an input signal Data of high frequency to an output signal Data of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Disclosed herein is a communication module, comprising a semiconductor chip in which channels for allowing signal converting means to convert current signals inputted from input terminals to voltage signals and outputting the same from output terminals respectively are arranged in parallel in plural form, and wherein the semiconductor chip is comprised principally of a semiconductor substrate in which a second semiconductor layer is provided on a first semiconductor layer with an insulating layer interposed therebetween, each of the signal converting means is formed in a channel forming region of the second semiconductor layer, which is defined for each channel, and the input and output terminals are formed on the channel forming regions of the second semiconductor layer with the insulating layer interposed therebetween. In the communication module, the first semiconductor layer is formed with resistivity smaller than that of the second semiconductor layer and fixed to a fixed potential, whereby the amount of transfer of noise power developed through the substrate can be lessened and crosstalk developed between adjacent channels can be reduced.

Communication module having a structure for reducing crosstalk

The present invention provides an optical interconnection receiving module that can cancel out the effect of cross talk noise caused by the input signal of another channel on the preamplifier side and the reference amplifier side, and provides suitable device structures for a bypass capacitor used to stabilize supply voltage and for a capacitance device used to cancel out the effect of cross talk noise caused by the input signal of another channel on the preamplifier side and on the reference amplifier side. According to the present invention, there are provided: a photodiode array comprising a plurality of photodiodes, each of which receives an optical signal on a plurality of channels and converts the optical signal into an electric signal; and a receiving circuit for distinguishing an input signal which comprises: a preamplifier for amplifying the electric signal converted from the optical signal by the photodiode array for each of the channels; a comparator; and a reference amplifier for generating reference voltage, wherein a plurality of capacitance devices each equivalent to the photodiode are formed on the semiconductor chip where the receiving circuit is formed, and each of the equivalent capacitance devices is connected between the input terminal of the reference amplifier and a supply voltage terminal.

Optical interconnection receiving module

An optical transmission apparatus includes a feedback amplification circuit having flat and wideband frequency characteristics in which the linearity within a band is excellent. As a result, frequency characteristics of the optical transmission apparatus are improved. A feedback amplification circuit is structured with an amplifier including a transistor receiving an input signal at the base thereof, a first feedback path including a feedback resistance provided between the input terminal and the output terminal of the amplifier, i.e., between the base and the collector of the transistor, in which a substantial phase margin added with the feedback gain thereof is set to a value obtained by adding a predetermined value to 60 degrees, and a second feedback path including an emitter follower circuit composed of a transistor and a constant current source and a feedback resistance, in which a substantial phase margin added with the feedback gain thereof is set to a value obtained by subtracting said predetermined value from 60 degrees or an approximate value thereof, as the basis.

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Ome, Japan

Satoshi Ueno