Renesas Electronics Corporation

Nec Corporation

Nec Electronics Corporation

Other

Satoshi Uchiya

Hiroyoshi Kudou

Taro Moriya

Hiroaki Katou

Yasutaka Nakashiba

Masayuki Furumiya

Fumiaki Futamura

Satoru Tokuda

A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.

Semiconductor device and method of manufacturing the same

A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.

Semiconductor device

To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.

Semiconductor device and method of manufacturing same

Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Semiconductor device with gate electrodes buried in trenches

A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Semiconductor device and manufacturing method thereof

A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Semiconductor device and method for manufacturing the same

A pad structureincludes an electrode pad (a first electrically conducting filmand a second electrically conducting film) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film) and a transparent resin film (a transparent resin) provided on the cover oxide film

Device comprising electrode pad

A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N-type.

Solid-state imaging device and method of driving the same

Electrode pad arrangement with open side for waste removal

A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.

Fabrication of solid-state imaging device having no transfer error of the signal charge from vertical horizontal charge-transfer section

Solid-state imaging device having no transfer error of the signal

A solid state image sensor device includes: a photoelectric conversion section having a first conductivity type semiconductor thin region and a second conductivity type semiconductor region in a surface area of a first conductivity type semiconductor layer; a signal electron transfer section formed within the surface area of the first conductivity type semiconductor layer, for transferring a signal electron generated at the photoelectric conversion section; and a signal electron read-out section formed over the surface area of the first conductivity type semiconductor layer, for reading-out the signal electron from the photoelectric conversion section to the signal electron transfer section. The first conductivity type semiconductor thin region is self-aligned with respect to the second conductivity type semiconductor region and this is achieved by using the same mask and controlling the angles of incidence in the ion implantation. It is possible to prevent occurrence of a potential well or a potential barrier which may otherwise occur under the electrode in case any misalignment develops during the photolithography process or any dimension deviation in the electrodes develops during the fabrication and it is possible to enhance the efficiency in which the signal electron is read-out from the photoelectric conversion section.

Method for fabricating solid state image sensor device having buried

A solid-state color imaging device comprises a semiconductor substrate having a plurality of optoelectrical conversion regions on a major surface of the substrate and an insulating layer on the major surface of the substrate. On the insulating layer is a light shielding layer having an array of holes respectively aligned with the optoelectrical conversion regions. On the light shielding layer is an anti-reflection layer to absorb light reflected from the light shielding layer. A color anti-blending layer and a color dyeing layer are successively formed on the anti-reflection layer. The color dyeing layer has an array of color filtering regions in positions which correspond respectively to the optoelectrical conversion regions.

Growing community of inventors

Kanagawa, Japan

Satoshi Uchiya