Nissan Motor Company Limited

Sanken Electric Co., Ltd.

Fuji Electric Co., Ltd.

Rohm Co., Ltd.

Other

National Institute of Advanced Industrial Science and Technology

Sharp Kabushiki Kaisha Corporation

Sumitomo Metal Mining Company, Ltd.

Nissan Arc, Ltd.

Satoshi Tanimoto

Shinji Sato

Kohei Matsui

Yoshinori Murakami

Mineo Miura

Noriaki Kawamoto

Yusuke Zushi

Takayuki Kitou

Hideyo Okushi

Masahiko Ogura

Toshiharu Makino

Satoshi Yamasaki

Hiromitsu Kato

Takashi Iseki

Norio Tokuda

Yasuo Tarui

Norihiko Kiritani

Hidekazu Tanisawa

Masato Takamori

Shinichi Morita

Yoshihiro Soutome

Yu Fukushima

A half-bridge power semiconductor module includes an insulating wiring board including a positive-electrode wiring conductor, a bridge wiring conductor, and a negative-electrode wiring conductor arranged on or above a single insulating plate in such a way as to be electrically insulated from each other. The back-surface electrodes of a high-side power semiconductor device and a low-side power semiconductor device are joined to the front sides of the positive-electrode wiring conductor and the bridge wiring conductor. Front-surface electrodes of the high-side power semiconductor device and the low-side power semiconductor device are connected to the bridge wiring conductor and the negative-electrode wiring conductor by a plurality of bonding wires and a plurality of bonding wires.

Half-bridge power semiconductor module and method of manufacturing same

A module () includes an insulating substrate (), a power semiconductor device (HT), a power semiconductor device (LT), a bridge terminal (B), a high-side terminal (H), and a low-side terminal (L). The bridge terminal extends from a surface wiring conductor (B) at a position between the power semiconductor devices (HT,LT). The high-side terminal extends from a high-side rear surface wiring conductor (H) at a position between the power semiconductor devices (HT,LT). The low-side terminal extends from a low-side rear surface wiring conductor (L) at a position between the power semiconductor devices (HT,LT). A surface electrode of the power semiconductor device (HT) and a rear electrode of the power semiconductor device (LT) are connected to the surface wiring conductor (B).

Half-bridge power semiconductor module and manufacturing method therefor

A half-bridge power semiconductor module has an insulating wiring substrate including a single insulating plate, and a positive electrode wiring conductor, a bridge wiring conductor, and a negative electrode wiring conductor disposed on or above the insulating plate while being electrically isolated from one another, at least one high side power semiconductor device having a rear surface electrode bonded onto the positive electrode wiring conductor, at least one low side power semiconductor device having a rear surface electrode bonded onto the bridge wiring conductor, a stand-up bridge terminal connected to the bridge wiring conductor, a stand-up high side terminal disposed between the high side power semiconductor device and the bridge terminal, and connected to the positive electrode wiring conductor, and a stand-up low side terminal disposed between the bridge terminal and the low side power semiconductor device, and connected to the negative electrode wiring conductor.

Half-bridge power semiconductor module and method for manufacturing same

In a heat insulating load jigof the present invention, a solder materialhaving a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chipand a temperature 100&#xb0; C. below the thermal resistance temperature is interposed between a circuit boardand the semiconductor chip; a heat insulating bodyis placed on an upper side of the semiconductor chipin this state; a metal weightis disposed on the heat insulating body; and load is applied to the semiconductor chipwhile the solder materialis melted and solidified.

Method for manufacturing semiconductor device, heat insulating load jig, and method for setting up heat insulating load jig

A semiconductor device according to the present invention, having an Au-based solder layer () sandwiched between a semiconductor element () and a Cu substrate () made mainly of Cu, in which the semiconductor device includes: a dense metal film () which is arranged between the Cu substrate () and the Au-based solder layer (), and has fine slits () patterned to have a predetermined shape in a plan view; and fine structures () with dumbbell-like cross section, which have Cu and Au as main elements, and are each buried in the Cu substrate (), the Au-based solder layer (), and the fine slits () of the dense metal film ().

Au-based solder die attachment semiconductor device and method for manufacturing the same

In this junction element, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer, prohibiting electrons present in an electrode layerto move into the semiconductor layer. For this reason, a majority of holes in a semiconductor layerdo not disappear by recombination with conduction electrons in the semiconductor layer, but reach the electrode layerwhile diffusing into the semiconductor layer. Accordingly, the junction elementcan serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor. The present invention is applicable to any semiconductor material in which at least one of a donor level and an acceptor level is located at a sufficiently deep position beyond a thermal excitation energy at an operating temperature, such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or boron nitride (BN). The present invention is also applicable to even a material having a shallow impurity level at room temperature, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or germanium (Ge), as long as operation is performed at such a low temperature that the thermal excitation energy can be sufficiently small.

Semiconductor device

A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

Method for manufacturing semiconductor device, and semiconductor device

A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

Semiconductor module

A switching circuit includes: a first switching element (Q); a resistor () inserted between a control electrode (G) of the first switching element (Q) and a control circuit () switching the first switching element (Q); and a first capacitor () and a second switching element () connected in series between the control electrode (G) of the first switching element (Q) and a low potential-side electrode (S) of the first switching element (Q). A high potential-side electrode of the second switching element () is connected to the control electrode (G) of the first switching element (Q). An electrode of the first capacitor () is connected to the low potential-side electrode (S) of the first switching element (Q). A control electrode of the second switching element () is connected to an electrode of the resistor () connected to the control circuit ().

Switching circuit and semiconductor module

A silicon carbide semiconductor device (), includes: 1) a silicon carbide substrate (); 2) a gate electrode () made of polycrystalline silicon; and 3) an ONO insulating film () sandwiched between the silicon carbide substrate () and the gate electrode () to thereby form a gate structure, the ONO insulating film () including the followings formed sequentially from the silicon carbide substrate (): a) a first oxide silicon film (O) (), b) an SiN film (N) (), and c) an SiN thermally-oxidized film (O) (,,). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) () and in a vicinity of the silicon carbide substrate (), and ii) in an interface between the silicon carbide substrate () and the first oxide silicon film (O) ().

Silicon carbide semiconductor device and method for producing the same

A silicon carbide semiconductor device (), includes: 1) a silicon carbide substrate (); 2) a gate electrode () made of polycrystalline silicon; and 3) an ONO insulating film () sandwiched between the silicon carbide substrate () and the gate electrode () to thereby form a gate structure, the ONO insulating film () including the followings formed sequentially from the silicon carbide substrate (): a) a first oxide silicon film (O) (), b) an SiN film (N) (), and c) an SiN thermally-oxidized film (O) (). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) () and in a vicinity of the silicon carbide substrate (), and ii) in an interface between the silicon carbide substrate () and the first oxide silicon film (O) ().

A silicon carbide semiconductor device (), includes: 1) a silicon carbide substrate (); 2) a gate electrode () made of polycrystalline silicon; and 3) an ONO insulating film () sandwiched between the silicon carbide substrate () and the gate electrode () to thereby form a gate structure, the ONO insulating film () including the followings formed sequentially from the silicon carbide substrate (): a) a first oxide silicon film (O) (), b) an SiN film (N) (), and c) an SiN thermally-oxidized film (O) (, 12). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) () and in a vicinity of the silicon carbide substrate (), and ii) in an interface between the silicon carbide substrate () and the first oxide silicon film (O) ().

A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.

Method of manufacturing silicon carbide semiconductor device

In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Growing community of inventors

Yokohama, Japan

Satoshi Tanimoto