Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Toshiba Electronic Devices & Storage Corporation

Satoshi Takaya

Shinobu Fujita

Hiroki Noguchi

Hiroaki Ishihara

Tetsufumi Tanamoto

Kazutaka Ikegami

Hiroaki Yoda

Katsuhiko Koui

Tomoaki Inokuchi

Shinichi Yasuda

Takao Marukame

Naoharu Shimomura

Masafumi Mori

Yuichi Ohsawa

Hideyuki Sugiyama

Keiko Abe

Yushi Kato

Kohei Onizuka

Susumu Takeda

According to one embodiment, an electronic circuitry includes a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupler.

Electronic circuitry and power converter

an electronic circuit according to an embodiment includes: a generation circuit generating a first clocksignal and a second clocksignal delayed from the first clocksignal; a first coupler transmitting one of the first and the second clocksignals by electromagnetic coupling; a first converter driven by the transmitted clocksignal and converting a first input signal into a first signal of a frequency corresponding to the transmitted clocksignal; a second coupler transmitting the first signal by electromagnetic coupling; a second converter converting the first signal into a second signal of a frequency corresponding to the first input signal with the other of the first and the second clocksignals; an output device outputting the second signal; and a protection circuit connected to a line through which the one of the first and the second clocksignals is transmitted between the first coupler and the first converter.

Electronic circuit and electronic apparatus

An electronic circuit according to the embodiment of the present invention includes a first circuit, a second circuit electrically insulated from the first circuit, and a transmitter transmitting a signal between the first and the second circuits. The first circuit receives an input signal, generates a first reference signal, and converts frequencies of the input signal and the first reference signal. The transmitter transmits the frequency-converted input signal and first reference signal to the second circuit. The second circuit converts the frequencies of the transmitted input signal first reference signal to obtain a restored input signal and a restored first reference signal, generates a second reference signal, calculates a gain to be adjusted of the restored input signal based on the restored first reference signal and the second reference signal to adjust the gain of the restored input signal.

An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

Electronic circuit, electronic apparatus, and method

According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Magnetic memory device

According to one embodiment, a magnetic memory device includes a first conductive layer, a first stacked body, and a controller. The first conductive layer includes a first region, a second region, and a third region between the first region and the second region. The first stacked body includes a first magnetic layer, a second magnetic layer provided between the third region and the first magnetic layer in a first direction crossing a second direction, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second direction is from the first region toward the second region. The controller electrically is connected to the first region, the second region, and the first magnetic layer. The controller performs at least first to third operations. In the operations, the controller sets the first stacked body to first to third resistance state.

According to an embodiment, a multiplier accumulator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.

Multiplier accumulator, network unit, and network apparatus

According to one embodiment, a magnetic memory includes: a memory area; a first memory unit disposed in the memory area and including h first magnetoresistive effect elements arrayed on a first conductive layer; and a first circuit configured to receive i-bit first data, convert the first data into j-bit (j=h) second data, and write the second data in the first memory unit. The second data includes m first values and (j&#x2212;m) second values, and m and j have a relationship given by 'j/2&#x2212;1&#x2264;m&#x2264;j/2+1'.

Magnetic memory including meomory units and circuits for reading and writing data and memory system

According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

Magnetic memory and memory system

According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.

Random number generator

A nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being connected to the second terminal, and a first driver electrically connected to the control terminal, applying a first potential to the control terminal in a first write operation, and applying a second potential larger than the first potential to the control terminal in a second write operation.

Nonvolatile resistance changing semiconductor memory using first and second writing operations

According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value.

Memory device and memory system

An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (Sto S), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S).

Authentication server, authentication system, and authentication method

According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor substrate, a first substrate area in the semiconductor substrate, a first cell unit in the first substrate area, the first cell unit including a first memory cell and a first transistor, and the first transistor having a control terminal connected to a first word line, using the first substrate area as a channel and supplying a read current or a write current to the first memory cell, and a substrate potential setting circuit setting the first substrate area to a first substrate potential when the read current is supplied to the first memory cell, and setting the first substrate area to a second substrate potential different from the first substrate potential when the write current is supplied to the first memory cell.

Nonvolatile semiconductor memory

According to one embodiment, a nonvolatile memory includes a memory cell, a write circuit generating a write current to change the memory cell from a first resistance value to a second resistance value, a first current generating circuit generating a first current based on the write current flowing through the memory cell, a second current generating circuit generating a second current based on the write current flowing through the memory cell, a hold circuit holding a first value generated based on the second current when the memory cell stores the first resistance value, a comparator comparing the first value with a second value generated based on a change of the first current while the memory cell changes from the first resistance value to the second resistance value, and a write current control circuit cutting off the write current based on a result of comparison of the comparator.

Growing community of inventors

Kawasaki, Japan

Satoshi Takaya