Fujitsu Semiconductor Limited

Fujitsu Corporation

Satoshi Takashima

Yasushige Ogawa

Hiroyuki Sugamoto

Yoshiyuki Ishida

Akihiro Miki

Shinya Ohhashi

A data transfer system includes a transmission circuit, which operates by a first clock signal, and a receiving circuit, which operates by a second clock signal different from the first clock signal. The transmission circuit includes an output circuit that outputs a poll signal, of which a level is logically inverted in accordance with a transmission timing of transmission data from the transmission circuit to the receiving circuit. A first signal generating circuit receives the transmission data at a plurality of timings and generates plural sets of reception data corresponding to the plurality of timings. A second signal generating circuit receives the poll signal at the plurality of timings and generates synchronous poll signals corresponding to the plurality of timings. A data selecting circuit compares levels of the synchronous poll signals with each other and selects one of the sets of reception data based on the comparison result.

Data transfer system, data transfer method, receiving circuit, and receiving method

An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Interface, memory system, and access control method

A semiconductor integrated circuit that acquires an external signal precisely in a high speed operation. The semiconductor integrated circuit includes an internal circuit for acquiring an external signal in response to an address acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the address acquisition signal.

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Kasugai, Japan

Satoshi Takashima