Matsushita Electric Industrial Co., Ltd.

Satoshi Takashima

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Takeshi Tanaka

Makoto Kojima

Hiroshi Kadota

Hiroyuki Morishita

Akira Miyoshi

Atsushi Ito

The parallel execution processorfetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unitassigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unitforms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor

Parallel execution processor and instruction assigning making use of group number in processing elements

A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Data processor and program for processing a data matrix

A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

Microprocessor

An internal step-down converter includes a potential difference detector and a cross-coupled amplifier. The potential difference detector detects and amplifies a potential difference between a reference voltage VREF and an internally-stepped-down supply voltage VINT. The cross-coupled amplifier receives the amplified output VDRV2 of the potential difference detector and the output VDRV of a current-mirror differential amplifier, which is applied as a control voltage to a driver implemented as a p-channel MOSFET. The cross-coupled amplifier regulates the amplitude of the control voltage VDRV substantially at the potential difference .vertline.VDD-VSS.vertline. between the external supply voltages. As a result, the load-current-handling capability of the driver can be considerably increased. While the load current ILOAD is relatively small, a control signal generator deactivates the potential difference detector and the cross-coupled amplifier to prevent the current from being consumed in vain. Accordingly, an internal step-down converter with enhanced load-current-handling capability is provided without increasing the layout area or the current consumed.

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Ibaraki, Japan

Satoshi Takashima