Motorola Corporation

Freescale Semiconductor,inc.

Satoshi Takahashi

Masami Aiura

Yuichi Nakatani

A power supply circuit that accurately generates output voltages with the same regulator includes a regulator for generating a first output voltage from an input voltage. A first switch circuit, connected to the regulator, selectively outputs the first output voltage of the regulator as a second output voltage from the power supply circuit. A pre-charge circuit, connected to the regulator and the first switch circuit, generates the second output voltage from the input voltage before the first output voltage of the regulator is output as the second output voltage while controlling the first switch circuit.

Method and circuit for generating output voltages from input voltage

A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.

Method and circuit for reducing regulator output noise

A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C through C . A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C -C , ranging from the second left-most current source cell C to the second right-most current source cell C , are used as cyclically selected cells. The remaining left-most current source cell C and right-most current source cell C are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.

Method of selecting cells for input code in a digital-to-analog converter

It is an objective to provide a digital-to-analog converter circuit that allows the value of the current output from each current source cell to be identical, regardless of the position of that current source cell relative to the power supply line. To ensure that the voltages supplied to the respective current source cells are identical, the power supply lines La and Lb are disposed in the form of a right triangle modified such that their line widths W and W become constantly narrower on one side depending on the position at which the power supply lines La and Lb are formed. The power supply lines La and Lb are also disposed such that their hypotenuses are opposite to each other.

Digital-to-analog-converter

An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.

Offset cancellation circuit

The A/D converter comprises a resistor series (30), a plurality of first comparators (1) and a plurality of second comparators (2). Resistor series (30) has a plurality of resistors(R) connected in series between two terminals to which predetermined reference voltages are applied. First comparator (1) compares a node voltage between resistors and an analog voltage signal to be compared. Second comparator (2) compares an average voltage of the two node voltages across each resistor R and the analog voltage signal. First and second comparators (1,2) are disposed alternatively.

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Sendai, Japan

Satoshi Takahashi