Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Chemical Corporation

Mitsubishi Kasei Corporation

Satoshi Sugawa

Michio Ito

Atsushi Yanagida

Shiro Hosotani

Hiroshi Kuranaga

A plurality of frames constituting a screen are divided into a plurality of groups such as G through G The number of pixels per line is made different between any adjacent two of these groups in such a manner that all lines included in each group will have the same number of pixels each. There should be a plurality of groups such as G through G which exclude lines having active pixels corresponding to image portions. Lines through having active pixels may have the same number of pixels each. The number of pixels per line is allowed to be different by 1 between any adjacent two of the groups.

Semiconductor integrated circuit

An output from an adder 10.sub.1, i.e., an output of a first bit plane is inputted to an adder 10.sub.6 through delay elements 2.sub.2 and 3.sub.0 and a multiplier 100.sub.0. On the other hand, input data X are inputted to multipliers C.sub.2.sup.1 to C.sub.0.sup.1 through a delay element 1.sub.0 and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives a partial product by the multiplier C.sub.2.sup.1 through a delay element 2.sub.3 and a partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and on the other hand a partial product by the multiplier C.sub.0.sup.1. An output from the adder 10.sub.3, i.e., an output of a second bit plane is inputted to the adder 10.sub.6 through a delay element 2.sub.5. The adder 10.sub.6 performs addition of the output from the adder 10.sub.3, i.e., the output of the second bit plane and the output from the adder 10.sub.1, i.e., the output of the first bit plane, to output the addition result. This structure allows reduction in the number of delay elements and adders, to achieve a filter circuit downsized in circuit scale.

Filter circuit with reduced number of delay elements and adders

A non-specific reaction suppressor for immunoassays having the formula: ##STR1## where R.sub.1, R.sub.2, Y, X, and R.sub.3 are defined in the specification.

Non-specific reaction suppressor

The invention relates to immunoassay reagents that are both sensitive and specific and which require no sample pretreatment. The invention reagents are particularly useful for assaying digoxin concentrations in patient sera. More particularly, the invention relates to methods and kits comprising (A) an immunoreactant immobilized on a support; and, (B) a buffer agent comprising (i) a buffering agent, (ii) sodium chloride, (iii) choline chloride, (iv) a polysaccharide, (v) fatty-acid-free serum albumin, and (vi) a non-specific reaction suppressor of the formula: ##STR1## wherein X is --NH--(CO)--NH--, --NH--(CS)--NH--, or --N.dbd.C.dbd.N--, R.sub.1 and R.sub.2, which may be the same or different, are C.sub.1 -C.sub.5 linear or branched alkyl groups, or R.sub.1 and R.sub.2, together with nitrogen, is ##STR2## or the metho-p-toluenesulfonate salt thereof, Y, which may be the same or different, is any of H, OH and halogen,

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Tokyo, Japan

Satoshi Sugawa