Adv Antest Corporation

Satoshi Sudou

Masakatsu Suda

Toshiyuki Okayasu

Shinya Sato

Masaru Doi

Naoyoshi Watanabe

Takuya Hasumi

Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Variable delay circuit, testing apparatus, and electronic device

A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.

Consumption current balance circuit, compensation current amount adjusting method, timing generator, and semiconductor testing apparatus

A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobes should be generated; a strobe generating circuit for generating the plurality of strobes; and an adjusting module for adjusting a timing of the strobe generating circuit's generating each of the strobes on the basis of the signal for adjustment.

Multi-strobe apparatus, testing apparatus, and adjusting method

A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay element coupled in parallel to the plural stages of first variable delay elements for delaying the reference clock signal, a phase comparator for comparing the phase of the reference clock signal delayed by the plural stages of first variable delay elements with the phase of the reference clock signal delayed by the second variable delay element, and a delay amount control unit for controlling the delay amount of each of the plural stages of first variable delay elements based on the comparison result of the phase comparator in order that the phase of the reference clock signal delayed by the plural stages of first variable delay elements is substantially the same as the phase of the reference clock signal delayed by the second variable delay element after predetermined cycles.

Variable delay circuit

A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount which is larger than the first delay amount, and a plurality of timing comparators for sampling a plurality of data signals delayed by the plural stages of first variable delay elements by the strobe signal delayed by the second variable delay element of the same stage, wherein the timing comparator includes a dynamic D-FF circuit for latching and outputting the data signal by its parasitic capacitance based on the strobe signal, a buffer for delaying the strobe signal, and a positive feed-back D-FF circuit for latching and outputting the output signal outputted by the dynamic D-FF circuit by its positive feed-back circuit based on the strobe signal delayed.

Timing comparator, data sampling apparatus, and testing apparatus

A clock recovery circuit includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a clock signal by a second delay amount which is larger than the first delay amount, a plurality of timing comparators for sampling a plurality of the data signals delayed by the plural stages of first variable delay elements with the clock signal delayed by the second variable delay elements of the same stages, a plurality of EOR circuits for performing exclusive OR operation on a pair of sampling results by a pair of the sequential timing comparators, and a recovery variable delay circuit for delaying the clock signal based on the operation result of the plurality of EOR circuits.

Clock recovery circuit and communication device

In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the avoidance of excessive enlargement in the scale of circuitry. A pair of an integer delay generation part and a fraction delay data generation part that are components of the semiconductor device testing apparatus is provided by the same number as that of pins of each semiconductor device under test, and a waveform control part is provided by the same number as that of the semiconductor devices under test for each of the pairs. In each waveform control part are generated a set pulse and a reset pulse for generating a test pattern signal to be applied to each of pins having the same attribute of the semiconductor devices under test, thereby to generate a test pattern signal. By applying individual data to each waveform control part instead of test pattern data, respective individual data can be written simultaneously in the semiconductor devices under test.

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Tokyo, Japan

Satoshi Sudou