Fujitsu Corporation

Pfu Limited

Satoshi Shinohara

Hirohide Sugahara

Akira Kabemoto

Toshiyuki Muta

Takatsugu Sasaki

Takayuki Shimamura

Yozo Nakayama

Jun Sakurai

Naohiro Shibata

Junji Nishioka

Hiroshi Ishikawa

Takeshi Horie

Toshiyuki Shimizu

Hiroaki Ishihata

Tadao Amada

Kyoichi Takada

Ken'ichi Ishizaka

A heat exchange device that is coupled to an electronic device that includes an electronic component that generates heat, the heat exchange device includes: a first-channel through which a first-coolant that cools the electronic component flows; a heat-exchange-unit that performs heat exchange between the first-coolant and a second-coolant; a second-channel through which the second-coolant-flows; a first-coolant-detection-unit that detects leakage of the first-coolant from the first-channel; a collection-unit that collects the first-coolant that is leaked from the first-channel; a storage-unit that is provided in the first-channel and supplies the stored first-coolant to the first channel; a recovery-unit that is provided between the collection-unit and the storage-unit; and a control-unit that causes the recovery-unit to recover the first-coolant that is collected by the collection unit, into the storage-unit when the first-coolant-detection-unit detects leakage of the first-coolant.

Heat exchange device, electronic system, and cooling method of electronic system

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Multiprocessor, memory accessing method for multiprocessor, transmitter

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Coherence apparatus for cache of multiprocessor

Growing community of inventors

Kawasaki, Japan

Satoshi Shinohara