National Semiconductor Corporation

Texas Instruments Corporation

Satoshi Sakurai

Sing W Chin

Ion E Opris

Bumha Lee

Bill C Wong

Jason Chin

Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.

Temperature tolerant input stages for circuits

A comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first transistor and the second transistor are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch is coupled to the first transistor and is configured to selectably enable the first transistor. The second switch is coupled to the second transistor and is configured to selectably enable the second transistor. The timing circuit is coupled to the first switch and the second switch and is configured to close the first switch responsive to a signal transition at an output of the comparator circuit and close the second switch a predetermined delay time after the first switch is closed.

Comparator hysteresis circuit

A circuit includes a first resistor coupled to a supply voltage node. The circuit further includes a first pair of transistors and a second pair of transistors. The first pair of transistors is coupled in series between the first resistor and an output node. The second pair of transistors is coupled in series between the output voltage node and a ground nod. A first capacitor is coupled in parallel across the first resistor.

Low-power high-speed Schmitt Trigger with high noise rejection

Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (v); a second transistor (Q) having a collector terminal coupled to an emitter terminal of the first transistor (Q); a third transistor (Q) having an emitter terminal coupled to an emitter terminal of the second transistor (Q) and to a ground node, a collector terminal coupled to a current source (I), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q); and a capacitor (C) coupled to the base terminals of the second and third transistors (Qand Q) and to a second input node (v), wherein the first and second input nodes (vand v) are differential inputs.

Load current compensation for analog input buffers

A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor switch device is coupled in series with the PAC to provide a circuit branch parallel with the signal path. The transistor switch device is configured to selectively open or close the circuit branch of the signal path to enable or disable, respectively, the adjustment of the phase of the signal on the signal path via the PAC. A nonlinear capacitance is coupled to a node interconnecting the PAC and the transistor switch device. The nonlinear capacitance is configured to vary inversely proportional with a capacitance of the transistor switch device with respect to the signal on the signal path and to linearize a total capacitance provided by the circuit branch when the circuit branch is open.

Linearization circuit for high frequency signal phase adjustment

A high-speed unity-gain input buffer steers the current that flows down a first path to an output node, and down a second path in response to an analog input signal. The current that flows down the second path is mirrored to sink a current out of the output node.

High-speed unity-gain input buffer having improved linearity and stability with a low supply voltage

Bias current generation systems are disclosed. In one embodiment, a bias current generation system comprises a proportional to absolute temperature (PTAT) current source generating a PTAT current, a constant current source generating a constant current, a first current mirror forwarding the PTAT current, a second current mirror forwarding an adjusted current, where the adjusted current is the constant current subtracted by the PTAT current if the constant current subtracted by the PTAT current is greater than zero or the adjusted current is zero if the constant current subtracted by the PTAT current is less than zero, a third current mirror forwarding the adjusted current and a fourth current mirror forwarding a bias current generated by subtracting the PTAT current from the adjusted current.

Power efficient and fast settling bias current generation circuit and system

Bias current generation circuits and systems are disclosed. In one embodiment, a gain boosting cascode system comprises a cascode based on a transconductance amplifier and a current buffer and a gain booster circuit coupled to the cascode optimally boosting a gain of the cascode by maintaining the transconductance amplifier and the current buffer in their respective saturation regions. The gain booster circuit is based on one or more feedback amplifiers coupled in series with a main voltage control transistor. The main voltage control transistor is maintained in a triode region, and the voltage at the drain of the main voltage control transistor can be set by passing an appropriate amount of current through the main voltage control transistor. This in turn would keep the transconductance amplifier and the current buffer in their respective saturation regions, thus generating the optimal gain for the gain boosted cascode system.

Gainboost biasing circuit for low voltage operational amplifier design

Bias current generation circuits and systems are disclosed. In one embodiment, a bias current generation system comprises a current generation circuit generating a first current based on a first voltage and an external resistor, a current mirror forwarding a second current proportional to the first current, and one or more bias current generation circuits with each circuit generating a bias current based on a second voltage over a resistance of a transistor device, where the transistor device is maintained in a triode region using a third voltage associated with the second current and where the resistance of the transistor device shares characteristics of a resistance of the external resistor.

Precision on chip bias current generation

A method and apparatus are arranged for minimizing the effects of capacitor mismatch errors in pipelined analog-to-digital converters (ADC). The virtual elimination of capacitor mismatch effects is achieved without trading comparator-offset margin by an appropriate selection of comparator circuits' reference signals and the inclusion of a plurality of capacitors that are switched into an appropriate feedback position. The appropriate feedback position in the switched capacitor amplifier circuit is determined based on the operating region. For each of k pipeline stage, a method includes: determining an operating region of a sampled analog input signal for a predetermined transfer curve, and computing digital code bits and an improved residue signal for this stage based on the determined operating region, and then computing a final conversion code from the digital code bits of the k pipeline stages.

Capacitor mismatch independent gain stage for differential pipeline analog to digital converters

A capacitor array of the present invention has a plurality of core capacitors arranged in a plurality of rows and a plurality of columns. A plurality of guard capacitors are arranged such that there is a guard capacitor at the beginning and end of each of the rows and columns of core capacitors. A plurality of fringe capacitors are arranged between the guard capacitors and the core capacitors. The top plates of the core capacitors and the top plates of the fringe capacitors are coupled to a first node of a circuit. The top and bottom plates of the guard capacitors and the bottom plates of the fringe capacitors are coupled to ground. The each of the bottom plates of the core capacitors are independently coupled to a respective independent node of the circuit. The various capacitors of the array and the means for coupling them are uniformly distributed such that each core capacitor is uniformly influenced by its adjacent structure. Thus, each core capacitor in the capacitor array has substantially matched primary and parasitic capacitances.

Matched capacitor array

A method and apparatus are arranged for minimizing the effects of capacitor mismatch errors in pipelined analog-to-digital converters (ADC). The virtual elimination of capacitor mismatch effects is achieved without trading comparator offset margin by an appropriate selection of comparator circuits' reference signals and the inclusion of a plurality of capacitors that are switched into an appropriate feedback position. The appropriate feedback position in the switched capacitor amplifier circuit is determined based on the operating region. For each of k pipeline stage, a method includes: determining an operating region of a sampled analog input signal for a predetermined transfer curve, and computing digital code bits and an improved residue signal for this stage based on the determined operating region, and then computing a final conversion code from the digital code bits of the k pipeline stages.

Capacitor mismatch independent gain stage for pipeline analog to digital converters

A comparator circuit for comparing a differential input signal to a reference signal. A differential MOS transistor pair is provided having respective gates for receiving the positive and negative components of the differential input signal. A tail current source is coupled to the common sources of the transistor pair, with the current magnitude being related to the reference signal magnitude. The first and second transistors are made differently, typically by making the sizes different, so that the gate-source voltages differ when the transistor currents are equal. A comparator stage provides a digital output which changes state when the transistor currents are equal, with the difference in gate-source voltage representing the comparator trip voltage, a trip voltage related to the magnitude of the reference signal.

Comparator circuit for comparing differential input signal with reference signal and method

An apparatus and method for providing a reference voltage which provides a signal indicating when the reference voltage has reached a desired stable condition. This signal is obtained by comparing two test voltages which are interrelated and also related to the condition of the reference voltage.

Apparatus and method for reference voltage generator with self-monitoring

A current generator circuit having an output current with a stable absolute magnitude and which is proportional to a temperature of about T Kelvin. An MOS transistor operating in the linear region produces a drain-source current related to the output current and is biased with a drain-source voltage related to the difference between the base-emitter voltage of a pair of bipolar transistors operating at different current densities. The temperature coefficient of the output current is ideal for biasing an amplifier circuit so as to maintain a minimum settling time over a specified temperature range.

Growing community of inventors

San Carlos, CA, United States of America

Satoshi Sakurai