Omnivision Technologies, Inc.

Satoshi Sakurai

Hiroaki Ebihara

Liang Zuo

Zhenfu Tian

Rui Wang

Yan Li

Yu-Shen Yang

Chengcheng Xu

Lihang Fan

Kenny Geng

Peter Bartkovjak

Tao Sun

Naoki Kitazawa

Nobuhiro Yanagisawa

Jiayu Guo

Tomoyasu Tate

Kohei Harada

Wen He

An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

Distributed ramp linearity compensation circuit

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

Adaptive correlated multiple sampling

A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

Dynamic current control for column ADC

A failure detection circuit for an image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive a signal from a bitline of a bitline array in an image sensor that includes an array of pixels with each pixel is coupled to at least one bitline of the bitline array. The output stage is coupled to generate an output voltage indicative of any of the second input nodes being lower than the reference voltage.

Column ASIL circuit for multiple bitlines in an image sensor

A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

Calibration circuit for ramp settling assist circuit in local ramp buffer circuit

A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.

Ramp settling assist circuit in local ramp buffer circuit

A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.

Gray code counting signal distribution system

An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N&#x2212;M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2. An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N&#x2212;M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N&#x2212;M MSBs of the second output.

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Cupertino, CA, United States of America

Satoshi Sakurai