Hitachi, Ltd.

Satoshi Ootomo

Takeo Yamada

Takashi Azuma

Masanori Ogino

Miyuki Ikeda

A digital convergence correction circuit for a CRT display unit deals with the problem of an excessive calculation time of the microprocessor expended for the vertical interpolation by using at least two pieces of ROM (read only memory) devices connected together. The circuit deals with the problem of a step variation of brightness by employment of a novel slope interpolation means which implements interpolation based on a continuous waveform of the first-order differential coefficient at the lattice points of the display screen and a curve interpolation means which forms a more superior convergence system. The circuit uses a blanking means to prevent abnormal states from appearing on the display screen during the transfer period of the digital convergence correction data of a new format at the switching of the scanning format for a video signal to be displayed. The circuit includes a two-dimensional interpolation means which evaluates a set of lattice point data of the new format based on the parameter of the new format from a set of lattice point data of the old format. Consequently, the circuit eliminates the need of having many expensive ROMs for each scanning line and for each format individually, allowing a smaller ROM capacity and a shorter format switching time, and moreover a reduced number of adjustment steps required for individual formats.

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Fujisawa, Japan

Satoshi Ootomo