Fujitsu Corporation

Satoshi Ohwada

Toru Kosugi

Takenao Takemura

A zero string error detection circuit which detects a specified number of zeros occurring in succession in bipolar data. The detection circuit has a relatively small gate size achieved by making the shift registers in the B8ZS or B6ZS code conversion circuit serve also for zero string monitoring. The zero string error detection circuit includes a pair of shift registers which receive serial bipolar data and convert it to parallel data composed of a specified number of bits, a code detector which, upon detecting a specific code from the parallel outputs of the shift registers, issues a reset signal to the shift registers to make the outputs of the shift registers zero, a zero string monitor which issue a zero string error detection signal when the outputs of the shift registers become zero, and a gate which inhibits the zero string monitor from issuing the zero string error detection signal during a specific period when the code detector issues a reset signal.

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Oyama, Japan

Satoshi Ohwada