Hitachi, Ltd.

Satoshi Oguni

Hitoshi Ueno

Eiki Kamada

Hirofumi Fujita

Morihide Nakaya

Yuko Ishibashi

Naoki Hirayama

Takushi Tamura

Shinichi Machida

Yasuhiro Kameda

Kazuhiko Sako

Susumu Kajita

Provided is a computer system in which power consumption of the system can be reduced and which can smoothly supply data for a request from a client and avoid increase in a failure rate. In the computer system, by maintaining a power activation threshold for activating a stopping server blade and load balance threshold for assigning the request to a server blade, a server blade whose power is activated but to which the request from the client is not assigned is previously arranged. Priorities of the server blades are maintained, and are periodically changed or are changed in accordance with operation information such as total operation time and the number of times of activation/stop. Further, by maintaining the power activation threshold and a power stop threshold, possibilities of the unbalance among the activated/stopped server blades and frequent control of the activation/stop only in a part of server blades are avoided.

Computer system with blade system and management server

An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.

Information processing apparatus and power saving memory management method with an upper limit of task area units that may be simultaneously powered

A method of deciphering ciphered data in which in parallel to a deciphering process for first ciphered data, a first chaining value to be used for deciphering second ciphered data is generated, by using the generated chaining value, a process of deciphering the second ciphered data is executed, and in parallel to a deciphering process for the second ciphered data, a second chaining value to be used for deciphering third ciphered data is generated.

Method of deciphering ciphered data and apparatus for same

A memory array area of a semiconductor chip is divided into a plurality of partial memories. Each partial memory is provided with a register. The distance between adjacent registers is set shorter than a maximum distance which that data can travel in the memory in one data transfer cycle defined by a clock signal. These registers are serially connected and provides a path through which addresses, input data, and control signals are transferred to desired partial memories in synchronism with the clock signal. Output data and status signals are also transferred through these registers to a memory output terminal in synchronism with the clock signal.

Memory with sequential data transfer scheme

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Yokohama, Japan

Satoshi Oguni