Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Satoshi Oguchi

Kazuyuki Miyazawa

Gen Murakami

Toshiyuki Sakuta

Masamichi Ishihara

Kunihiko Nishi

Aizo Kaneda

Shozo Nakamura

Masao Mitani

Hiroyuki Uchiyama

Ryoichi Hori

Yasushi Takahashi

Hisashi Nakamura

Hidetoshi Iwai

Masaya Muranaka

Hiromi Matsuura

Yoshihisa Koyama

Hidetomo Aoyagi

Shigetoshi Sakomura

Haruo Ii

Takeshi Kizaki

Kazumasa Yanagisawa

Ichiro Anjoh

Hiroshi Satoh

Yasunori Yamaguchi

Yasuhiro Kasama

Eiji Miyamoto

Kazuya Ito

Tetsu Udagawa

Youichi Matsuno

Atsusi Nozoe

Toshitugu Takekuma

Atsushi Hiraishi

Hideyuki Aoki

Sadayuki Ohkuma

Toshitugu Takemuma

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

Semiconductor device

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Sealed stacked arrangement of semiconductor devices

A semiconductor memory device facilitated with a test circuit having a simple construction of a plurality of MOSFETs having their individual gates connected with a plurality of word lines in a memory array; and a testing pad for detecting the presence of an electric current flowing between the sources and drains of the plurality of MOSFETs. If the word line is short-circuited to the power supply to achieve an intermediate potential equal to or higher than the threshold voltage of the MOSFETs, an electric current will flow through the MOSFETs so that the presence of the short-circuit between the word lines and the power supply can be accurately detected.

Semiconductor memory device having detection circuitry for sensing

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Multi-chip semiconductor package

A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.

Static RAM

Growing community of inventors

Ohme, Japan

Satoshi Oguchi