Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Elpida Memory, Inc.

Satoshi Ogino

Takahiro Maruyama

Shigenori Sakamori

Kazumasa Yonekura

Tadashi Yamaguchi

Kenji Kawai

Tomonori Okudaira

Keiichiro Kashihara

Nobuo Fujiwara

Toshiaki Tsutsumi

Hajime Kimura

Kazuyuki Ohmi

Akemi Teratani

Yoshihiro Miyagawa

Kotaro Kihara

Yuzo Irie

To improve the performance of semiconductor devices. Over an n-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

Semiconductor device and method of manufacturing same

A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

Method for manufacturing a semiconductor device including a silicon film

A plasma reactor is provided for achieving extension of etching parameters to reduce charge-up shape anomaly and to improve selectivity, uniformity and workability in a dry etching process. An RF power fluctuates in cycles, each one of the cycles including first and second subcycles ( ), ( ) with different frequencies. The RF power in the first subcycles ( ) is higher in frequency than that in the second subcycles ( ). A charge accumulated during the first subcycles ( ) in which the RF power of high frequency is applied can be relieved during the second subcycles ( ) in which the RF power of low frequency is applied. At the same time, deterioration in an etching rate occurring with the application of only the RF power of low frequency can be relieved by applying the RF power of high frequency during the first subcycles ( ).

Plasma reactor

Plasma reactor and method

A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO,layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.

Semiconductor device and manufacturing method thereof

Provided is a plasma processing apparatus capable of extending an etching parameter to reduce charge-up shape anomalies in dry etching and to enhance etching performance such as selectivity, uniformity, processability or the like. A microwave is controlled to be modulated in frequency and is introduced into a chamber. An ECR face is moved between two positions according to the frequency of the microwave.

Plasma processing apparatus

Growing community of inventors

Tokyo, Japan

Satoshi Ogino