Sanyo Electric Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Satoshi Noro

Shin-ichiro Tomisawa

Tomofumi Watanabe

Satoshi Yokoo

Toshiyuki Shutoku

Hiroki Nagai

Kazuhiko Kondo

Takuya Shiraishi

Yutaka Tamura

Yoshio Hosokawa

An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals.

Multi-chip package semiconductor device

A data processor compatible for use with a CD and a DVD includes a first modulation circuit for modulating recording data for recording on a CD to generate first modulated data. A second modulation circuit modulates recording data for recording on a DVD to generate second modulated data. A write signal generation circuit generates a first write signal, which is written to the CD, from the first modulated data, and a second write signal, which is written to the DVD, from the second modulated data. The write signal generation circuit is commonly used for the CD and the DVD to reduce the circuit area of the data processor.

Data processor used in a plurality of optical disk recording mediums

A decoder having improved accuracy for reading data. The decoder decodes reproduced data including preamble data, to which a first synchronization pattern is added, and information data, which follows the preamble data and to which a second synchronization pattern is added. The decoder includes a memory for storing a first, second, and third comparison patterns respectively corresponding to the first synchronization pattern, the preamble data, and the second synchronization pattern. A comparison circuit compares the first synchronization pattern, the preamble data, and the second synchronization pattern respectively with the corresponding comparison patterns. A determination circuit generates a start signal to start decoding when at least two of the first synchronization pattern, the preamble data, and the second synchronization pattern match the corresponding comparison pattern. A decoding circuit starts error correction of the reproduced data in response to the start signal.

Decoder

An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the access circuit may be switched between one byte, one word, and two words. The switching of the access data unit is performed in accordance with a data unit designation signal generated by decoding address data, which is provided to a control unit, with an address decoder. The memory interface receives a request signal that is in accordance with the data unit designation signal from a request generator and accesses the buffer memory in the access data unit that is in accordance with the request signal.

Access circuit with various access data units

A decoder for improving the reliability of synchronization pattern detection. The decoder includes a synchronization circuit for detecting a synchronization pattern from LPP data and wobble data. A first frame counter is reset when a synchronization detection circuit detects the synchronization pattern of a first sector and counts the number of frames of data until the synchronization pattern of the next sector is detected. A comparison circuit compares a count value of the first frame counter with a first reference value, which corresponds to the number of frames for one sector. A determination circuit determines whether or not the detected synchronization pattern is proper based on the comparison result of the comparison circuit.

A road path searching apparatus applicable to a car navigation system is disclosed. Road map data with different level of detail for defining a predetermined area is stored previously in a memory device. First, nodes Nai and Nbj adjacent to each of the search nodes Pa and PB are detected based on map data having a high level of detail. When nodes Nai and Nbj exist on a map of a lower level of detail, a map of one lower level of detail is selected as a map to be used in the searching process. Accordingly, as following searching process is performed based on the map data of lower level of detail, required processing time is reduced.

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Gifu-ken, Japan

Satoshi Noro