Fujitsu Corporation

Satoshi Nojima

Yuji Nomura

Takeshi Yasuie

Akira Takeyama

Susumu Tominaga

Hideo Suzuki

Masanobu Morinaga

Noriyuki Fukuyama

Naoki Oguchi

Hideaki Miyazaki

Masaaki Wakamoto

Tsuneo Katsuyama

Kazuo Sakagawa

Mitsuru Tsuboi

Kenshi Tazaki

Norihiro Aritaka

Teruyoshi Mita

In a relay device or the like in which a speed changes from a high speed to a low speed, a packet residence (packet transfer wait) occurs when a packet string in which packet intervals are shortened arrives. When a packet discard occurs before passing through the relay device or the like, a packet interval having been lengthened by the packet discard is shortened by the relay device or the like for transferring packets. When a packet discard occurs after passing through the relay device or the like, a packet interval having been lengthened by the packet discard remains unshortened for transferring packets. Therefore, by observing at terminals the packet discard and the packet interval on the occasion of the packet discard, whether the packet discard has occurred in the high speed section or the low speed section is specified.

Packet discard point probing method and device

A computer-readable recording medium recording a program capable of accurately analyzing the cause of a performance fault at the very end point of a client system, server system, etc. Outgoing and incoming packets are captured during execution of a communication application to measure a round trip time, and a communication window size of the transmitting source is estimated based on the captured incoming packets. A throughput estimate is calculated from the round trip time and the communication window size, and the estimated value and actual measured value of the throughput are displayed on, for example, a display, together with various other communication parameters including the communication window size and the round trip time, whereby the cause of a performance fault can be accurately located by quantitative analysis.

Recording medium, fault analysis device and fault analysis method

An end equipment (including a terminal equipment and a router) executes a destination address resolution of a data packet. In a network layer, when a packet transmitter detects that a direct route of an input packet is not registered in a routing table a path manager transmits an inquiry packet, demands a preparation of a point-to-point logical interface of the direct route based on a data link layer address of the destination included in the received response packet, and registers the prepared logical interface in the routing table.

End equipment and router

In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit as congested state information. A route identifying unit receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit to thereby identify the route accommodated within its node. A route control unit carries out control of the congested state of the identified route on the basis of the received congested state information. As described above, since traffic passing the transmission line is classified into 'route' and grouped, an object whose congestion is to be supervised is limited and each node can regulated only the traffic passing the transmission line in which the congestion occurred in units of routes.

Route regulating apparatus

A packet switching system having a matrix switch including input packet transfer buses and output packet transfer buses. Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.

Packet switching system having bus matrix switch

A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.

Data transfer system having transfer discrimination circuit

A loop transmission system and a method of controlling the loop-back condition thereof. The loop transmission system comprises a plurality of node stations, a supervisory station, and two duplicate loop transmission lines which transmit signals in opposite directions. In the loop transmission system, the supervisory station first sends out loop-back commands via both of the duplicate loop transmission lines when faults are detected on both of the duplicate loop transmission lines at the same time. Each of the node stations establishes a loop-back path while retaining a connection path to a succeeding node station upon the receipt of a loop-back command. The loop-back path is released only in the node stations which receive signals normally from both of the duplicate loop transmission lines when the supervisory station sends release commands to the node stations after sending the loopback commands.

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Kawasaki, Japan

Satoshi Nojima