Fujitsu Corporation

Satoshi Nemoto

Yukio Suda

Hiroshi Tomonaga

Takashi Kuwabara

Masahiro Shioda

Hideo Abe

Hidenori Sugai

Masayuki Tanaka

Kazuto Nishimura

Akihiro Hata

Toshinori Koyanagi

Yasuhiro Murakami

Yuji Kamura

Hideo Sunaga

Masaki Kubo

Shigeo Handa

Shuji Sakakura

Hiroyuki Nishimura

Shigetoshi Nakai

A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis of a memory with a predetermined period; executing a write operation and a read operation of the signal data on the memory at a timing of a second clock signal that is higher in rate than the first clock signal within the diagnosis period; executing at least one of operations included in the diagnosis of the memory using diagnosis data at a timing of the second clock signal during a period responsive to a difference between a number of first clock pulses of the first clock signal within the diagnosis period and a number of second clock pulses of the second clock signal within the diagnosis period; and diagnosing the memory by repeating the diagnosis period by a plurality of times.

Diagnosis method for diagnosing memory, transmission apparatus, and computer-readable recording medium

An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.

Apparatus and method for switching a packet

Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.

Switching device and switching method

In a packet relay method and device which can reduce a congestion of switching even when segment data are concentrated, segment data dividing portions respectively extract a destination address and a packet length from received packets, divide the packets into predetermined length data based on each packet length, and generates location information indicating locations in the packets respectively for the data. The segment data dividing portions add segment headers in which the location information, the destination address, and an address of its own device as a source address are set are added to each of the data, generate segment data, and provide the segment data to switches within a switch card in parallel.

Packet relay method and device

A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Signal processing circuit, interface unit, frame transmission apparatus, and segment data reading method

A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

Memory control device

A packet transmission device that is connected to a plurality of communication lines, and transmits a packet received, includes a failure detecting unit that monitors a condition of the communication lines, and detects a failure in the communication lines; and a packet transmitting unit that transmits, when the failure detecting unit detects a failure in a communication line, and when a packet having a same transmission-destination address as an address corresponding to a port of the communication line in which the failure has been detected is received, the packet from all preset ports.

Packet transmission device and packet transmission method

A non-interruptive protection switching device which performs protection switching in a more efficient and robust way. The device has a working-channel signal storage unit to store data signals received through a working channel. Multiframe synchronization timings are detected by a working-channel multiframe synchronization controller, which provides a working-channel multiframe sync detection pulse signal when the main signals are in a normal condition and stops it when the channel is disrupted. A working-channel write controller controls every write access to the working-channel signal storage unit, generating a write pulse signal therefor. The working-channel write controller also produces working-channel write phase data by identifying a phase difference of the detected multiframe synchronization timing with respect to a reference phase signal. The generation of this write pulse signal is based on the multiframe sync detection pulse signal when the working-channel multiframe sync detection pulse signal is available, or on a free-running timebase when it is stopped. The stored data in the working- and protection-channel signal storage units are read out simultaneously, under the control of a read controller which produces read pulses from the write phase data.

Non-interruptive protection switching device and network system using the same

A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.

Time slot assignment circuit

A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.

Growing community of inventors

Kawasaki, Japan

Satoshi Nemoto