Nec Corporation

Patent Technology Development Inc.

Satoshi Nakazato

Mitsuo Suzuki

Syuichi Oka

Akinori Tsuruda

Yasuhiro Kawano

It is intended to provide a novel oligopeptide which can be relatively easily produced, has not only a hair growth-stimulating effect but also an effect of promoting the growth of epithelial cells (for example, skin regeneration) and can easily pass through the horny layer to thereby reach the desired target cells in which its effects are to be exerted. Namely, water-soluble oligopeptides containing a proryl isoleucyl glycyl unit or an isoleucyl glycyl serine unit and having from 3 to 7 amino acids and water-soluble salts thereof.

Epithelial cell growth promoter

In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided, a logic function is allotted to the cells, the number of series connection stages of the cells within an evaluation period determined by a clock cycle of the clock signal is found, and a judgment is made as to whether restrictions can be met by arranging the cells on the semiconductor integrated circuit device and performing delay calculations in a case where the number of series connection stages does not exceed a prescribed number of stages. When the restrictions are met, the whole processing comes to an end. When the restrictions are not met, modifications are made.

Semiconductor integrated circuit device and design method thereof

A multiport cache memory is provided which enables reduction of a probability of bank contention which will occur when a plurality of read operations are executed simultaneously, and an access control system of the multiport cache memory.

Multiport cache memory which reduces probability of bank contention and access control system thereof

A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the respective CPUs are grouped into a master CPU which issues a vector processing instruction to other CPUs and slave CPUs operating as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU, the master CPU including a memory access control unit for issuing said vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring said instruction to all the CPUs including its own CPU through a bus, and the master CPU and the slave CPU including a vector processing instruction control unit for comparing issuing source CPU information contained in a vector processing instruction and master CPU information set at its own CPU and conducting instruction issuance based on the vector processing instruction when the information accord with each other and invalidating the vector processing instruction when the information fail to accord with each other.

Shared memory type vector processing system, including a bus for transferring a vector processing instruction, and control method thereof

A buffer is provided that has a high access time and operates with reduced power consumption. The buffer includes n write word line registers ( ), each of which an output is directly connected to a word line driver. Thus, a word line is driven to access a memory cell array. All the word line registers are cascaded in a ring form. The write START signal acting as a synchronous set input is input to the write word line register ( ) corresponding to the least significant address. The write strobe (STB) signal is input to the write word line registers connected in a ring form. When the write strobe signal is active, the write word line registers operate like a shift register. When the write strobe signal is not active, all the write word line registers hold a current value.

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Tokyo, Japan

Satoshi Nakazato