Fujitsu Corporation

Fujitsu Semiconductor Limited

Satoshi Nakai

Jusuke Ogura

Masato Suga

Kazushi Fujita

Kanetake Takasaki

Junichi Mitani

Shinji Sugatani

Ryota Nanjo

Mitsugu Tajima

Jun Sakuma

A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Method of manufacturing semiconductor integrated circuit device

A method of manufacturing a semiconductor device whereby, even in cases where ions are implanted into a shallow region of a semiconductor substrate when a deep well is formed, the influence of the ions on a MOSFET can be removed, thereby eliminating the need for increasing the chip area. A photoresist with a thickness matching the wavelength of exposure light is formed over the semiconductor substrate and then is exposed to the exposure light to form a photoresist pattern with an opening corresponding to a region for forming a first well. Subsequently, using the photoresist pattern as a mask, ions are implanted to form the first well, and after the photoresist pattern is removed, an epitaxial layer is grown over the semiconductor substrate. Consequently, the deep well is virtually located deeper in level than at the time of the ion implantation by an amount corresponding to the thickness of the epitaxial layer.

Method of manufacturing semiconductor device and semiconductor device

A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Semiconductor device

The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region.

Semiconductor device and method of fabricating the same

A method for manufacturing a semiconductor device includes: forming a first photoresist pattern on a second hard mask by use of ArF; forming first and second openings in the second hard mask by use of the first photoresist pattern as an etching mask; forming third and fourth openings in a first hard mask under the first and second openings; forming a partial trench (first trench) and a trench for a full trench (second trench) in an SOI substrate (semiconductor substrate) under the first and second openings; and forming the trench for a full trench into a full trench by etching the trench for a full trench through the fourth opening exposed through a third window of a second photoresist pattern.

Method for manufacturing a semiconductor device

First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.

Semiconductor device and its manufacture method

A process for the preparation of a high dielectric thin film. A tantalum oxide film is formed on a substrate at a temperature of from 400.degree. to 850.degree. C. by means of an electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD) method. A high dielectric film having little leakage current, good surface flatness and good step coverage is obtained.

Process for the preparation of a high dielectric thin film using ECR

A CVD apparatus comprising a reaction chamber in which reaction gas is supplied from above the substrate supported on the susceptor plate and exhausted uniformly from a plurality of circumferentially spaced gas exits, and infrared light heats the substrate from below the substrate via an infrared light transparent window arranged between the source of infrared light and the susceptor plate. A second infrared light transparent window with a central opening is arranged between the first infrared light transparent window and the susceptor plate. Nitrogen gas or an inert gas is supplied from a portion between the first and second infrared light transparent windows and flows through a plurality of circumferentially spaced gas passages arranged at the juncture of the susceptor plate and the peripheral wall of the reaction chamber to the gas exits. The gas passages are coordinated with the gas exits so that the flow of the reaction gas is less disturbed by the flow of the second gas.

Growing community of inventors

Kawasaki, Japan

Satoshi Nakai