Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Satoshi Mitsugi

Shinya Nunoue

Hiroshi Katsuno

Toshihide Ito

Toshiyuki Oka

Shinji Yamada

Hayato Goto

Kouichi Ichimura

Hiroshi Ono

Yasuo Ohba

Naoharu Sugiyama

Takashi Sato

Kei Kaneko

Hung Hung

Mitsuhiro Kushibe

Jongil Hwang

Tomonari Shioda

Taisuke Sato

Yukiyasu Arisawa

Takeshi Suto

In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.

Alignment mark, imprinting method, manufacturing method of semiconductor device, and alignment device

In an alignment mark of an embodiment, a first pattern has a periodic structure in a first direction on a surface of an original or a surface of a substrate and extends in a second direction, and a second pattern has a periodic structure in a third direction on the surface of the original or the surface of the substrate and extends in a fourth direction. The first direction and the third direction are parallel to each other. A period in the first direction of the periodic structure of the first pattern is equal to a period in the third direction of the periodic structure of the second pattern. At least one of the first pattern and the second pattern has a periodic structure in a fifth direction orthogonal to the first direction and the third direction on the surface of the original or the surface of the substrate. At least one of the second direction and the fourth direction is oblique with respect to the fifth direction.

Alignment mark, imprinting method, and manufacturing method of semiconductor device

According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.

Imprint apparatus and imprint method

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.

Semiconductor light emitting device

According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part.

According to one embodiment, a semiconductor light emitting device includes a first metal layer, a second metal layer, a third metal layer, a semiconductor light emitting unit and an insulating unit. The semiconductor light emitting unit is separated from the first metal layer in a first direction. The second metal layer is provided between the first metal layer and the semiconductor light emitting unit to be electrically connected to the first metal layer, and is light-reflective. The second metal layer includes a contact metal portion, and a peripheral metal portion. The third metal layer is light-reflective. The third metal layer includes an inner portion, a middle portion, and an outer portion. The insulating unit includes an first insulating portion, a second insulating portion, and a third insulating portion.

A semiconductor light emitting element includes a substrate and a stacked body. The stacked body is aligned with the substrate. The stacked body includes first and second semiconductor layers, a light emitting layer, and first and second electrodes. The first semiconductor layer has a first face including first and second portions. The first portion is provided with a plurality of convex portions. The second portion is aligned with the first portion. The second semiconductor layer is provided facing the second portion. The light emitting layer is provided between the second portion and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the light emitting layer. An interval of each of the convex portions is no less than 0.5 times and no more than 4 times a wavelength of a light emitted from the light emitting layer.

Semiconductor light emitting element and method for manufacturing the same

According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer.

According to one embodiment, a quantum computer includes a crystal, an optical resonator, and a light source. A host crystal included in the crystal satisfying three conditions a first condition that maximum phonon energy of the host crystal is low, and so that a homogenous broadening of aF(1) level of the Prion resulting from relaxation due to phonon emission is smaller than respective hyperfine splits of aH(1) level and theF(1) level of the Prion, a second condition that a site of the Prion does not have inversion symmetry, and the Prion has a Stark level in which theH(1) level and theF(1) level of the Prion are not degenerate, and a third condition that each atom in the host crystal has no electronic magnetic moment.

Quantum computer and quantum memory

According to one embodiment, a semiconductor light emitting device includes a metal layer, a stacked structural body, a first electrode, a pad electrode, a first conductive layer, a second conductive layer and an insulating layer. The metal layer includes a major surface having a first region, a second region, a third region and a fourth region. The stacked structural body includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The first semiconductor layer includes a first portion and a second portion. The second semiconductor layer is provided between the first region and the first portion. The first electrode is provided between the second region and the second portion. The pad electrode is provided on the third region. The first conductive layer is provided between the second region and the first electrode and between the third region and the pad electrode.

According to one embodiment, a semiconductor light emitting element includes a semiconductor layer, a first conductive layer, and a second conductive layer. The second conductive layer is provided between the semiconductor layer and the first conductive layer. A light transmittance of the second conductive layer is higher than a light transmittance of the first conductive layer. An extinction coefficient of the second conductive layer is 0.005 or less.

Semiconductor light emitting element

According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a dielectric layer, a first electrode, a second electrode and a support substrate. The first layer has a first and second surface. The second layer is provided on a side of the second surface of the first layer. The emitting layer is provided between the first and the second layer. The dielectric layer contacts the second surface and has a refractive index lower than that of the first layer. The first electrode includes a first and second portion. The first portion contacts the second surface and provided adjacent to the dielectric layer. The second portion contacts with an opposite side of the dielectric layer from the first semiconductor layer. The second electrode contacts with an opposite side of the second layer from the emitting layer.

According to one embodiment, a semiconductor light emitting device includes a stacked structure body, first and second electrodes. The stacked structure body includes first and second semiconductor layers and a light emitting layer provided between the second and first semiconductor layers, and has first and second major surfaces. The first electrode has a first contact part coming into contact with the first semiconductor layer. The second electrode has a part coming into contact with the second semiconductor layer. A surface of the first semiconductor layer on a side of the first major surface has a first part having a part overlapping a contact surface with the first semiconductor layer and a second part having a part overlapping the second semiconductor layer. The second part has irregularity. A pitch of the irregularity is longer than a peak wavelength of emission light. The first part has smaller irregularity than the second part.

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Kanagawa-ken, Japan

Satoshi Mitsugi