Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Satoshi Misaka

Kenichi Osada

Tetsuya Yamada

Makoto Saen

Shinjiro Yamada

Keisuke Toyama

Yusuke Kanno

Naohiko Irie

Kazuo Aisaka

An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Information processing device which specifies a waiting time until execution of a given event and makes a system call

A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Semiconductor integrated circuit device

Power consumption reduction and quicker interruption response in an information processing device utilizing a first timer and a second timer wherein the second timer is only conditionally activated

To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

Semiconductor integrated circuit device and power consumption control device

A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

Semiconductor integrated circuit device for real-time processing

An information processing system that can reduce its power consumption by means of robust power controlling even upon occurrence of an interruption/exception processing. If it is found that there is no task set in the ready state as a result of watching the number of tasks set in the ready state by the RTOS or ready state watching task, the system controls the RTOS or ready state watching task so as to lower the power while the current active task controls the power according to the preset WCET of each application slice. On the contrary, if there is any task set in the ready state, the system controls so as to raise the power and the current active task comes to control the power according to the virtual WCET that is earlier than the WCET of each application slice. And, if there is no task set in the ready state and there is no current active task, the system controls so that the RTOS or both of the ready state watching task and sleep task lower the power. This is why the present invention can reduce the power consumption of the subject information processing system.

System for adjusting a clock frequency based on comparing a required process times and a worst case execution times and adjusting a voltage and clock frequency based on a number of ready state application tasks

On the occasion of returning an error code to an application program to be executed under different execution environments of a computing system, it is requested to fully utilize a system of the existing instruction set to improve the ROM efficiency in the implementation of its common code and to eliminate useless insertion of instruction. For this purpose, in the present invention, a common error code to be returned, from the program to be used to be independent on different OS, to the execution program corresponding to the application program is determined as a value in the range of numerical value to be set with the instruction set of CPU and the defined instruction to load immediate value and thereby the common error code is held within the instruction code of the instruction to load immediate value. Particularly, a value of common error code is determined within the range where the MSB of the setting part of the instruction to load immediate value becomes zero (0).

Growing community of inventors

Kokubunji, Japan

Satoshi Misaka