Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Metals, Ltd.

Satoshi Meguro

Kazuhiro Komori

Shuji Ikeda

Hitoshi Kume

Toshiaki Yamanaka

Toshiaki Nishimoto

Naotaka Hashimoto

Atsuyoshi Koike

Yoshiaki Kamigaki

Koichiro Ishibashi

Yoshio Sakai

Kouichi Nagasawa

Katsuro Sasaki

Hideaki Yamamoto

Osamu Minato

Nobuyuki Moriwaki

Norio Suzuki

Soichiro Hashiba

Makoto Motoyoshi

Isamu Kuramoto

Yutaka Kobayashi

Atsushi Hiraishi

Seigou Yukutake

Shigeru Takahashi

Takashi Hashimoto

Takaaki Hagiwara

Kiyofumi Uchibori

Toshihisa Tsukada

Toru Kaga

Shigeru Honjou

Toshiaki Masuhara

Kotaro Nishimura

Sho Yamamoto

Kousuke Okuyama

Nobuyoshi Tanimura

Masaharu Kubo

Masayuki Kojima

Isamu Kobayashi

Toshifumi Takeda

Sadayuki Morita

Hisao Katto

Osamu Yamashiro

Yasunobu Kosa

Masahiro Ogata

Hisahiro Moriuchi

Kazuyuki Suko

Kyoichiro Asayama

Fumiyuki Kanai

Yasuo Kiguchi

Ken Uchida

Ryuuji Shibata

Kikuo Sakai

Youichi Matsumoto

Kanji Yoh

Kiyoshi Nagai

Toshiro Aoto

Harumi Wakimoto

Hideo Meguro

Eri Fujita

Kouichi Kusuyama

Hideaki Takahashi

Hideo Miura

Masataka Kato

Takeshi Wada

Tetsuo Adachi

Yoshifumi Kawamoto

Minoru Fukuda

Satoru Ito

Toshimasa Kihara

Shigeo Fujii

Eiji Takeda

Tadashi Muto

Masaaki Aoki

Takashi Nishida

Terunori Warabisako

Shoji Hanamura

Koichi Nagasawa

Tokumasa Yasui

Yuji Hara

Seiichi Isomae

Hiroyuki Mima

Kazutaka Narita

Toshiya Uenishi

Toshiko Koizumi

Toshihisa Tsukuda

Joh Nakajima

Toshihiro Ifuka

A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

Semiconductor integrated circuit device having single-element type non-volatile memory elements

Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets

To suppress oxidation of the inner walls of element isolation grooves otherwise occurring during thermal oxidation processes, a nitrogen introducing layer, that has a lower diffusion coefficient relative to an oxidizing agent, is formed at the surface portion of a silicon oxide film buried within an element isolation groove. This nitrogen introduced layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or the like) in vapor phase from diffusing into the silicon oxide film during thermal processing steps. The nitrogen introduced layer is formed by performing nitrogen ion implantation into the entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen that has been doped.

Semiconductor integrated circuit device and method of fabricating the same

Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs

An inductive magnetic head used for high-density recording having such a construction that prevents magnetic leakage near a magnetic pole at the tip of the magnetic core and reduces magnetic resistance or reluctance at an upper magnetic core front portion is disclosed. An upper magnetic core facing a lower magnetic core with a non-magnetic gap layer interposed therebetween comprises an upper magnetic core front portion near a magnetic pole, and an upper magnetic core rear portion at the rear portion. The front portion has a parallel portion having a width almost equal to the track width extending from the magnetic pole toward the rear end of the front portion, and a sector at the rear of an apex. The front portion has a non-magnetic gap with the lower magnetic core at an area between the magnetic pole and the apex, and the gap between the front portion and the lower magnetic core is wider than the magnetic gap at the rear of the apex. The tip portion of the upper magnetic core rear portion is overlapped and connected to the upper magnetic core front portion on the medium-facing surface side of the apex, extending therefrom to the upper part of a coil and a coil insulating layer.

Magnetic head having separated upper magnetic cores for avoiding magnetic saturation and manufacturing method of same

A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Semiconductor integrated circuit device

A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs

Semiconductor memory device having driver and load MISFETs and capacitor elements

A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode.

Non-volatile semiconductor memory device

A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region, for example, during an erase operation of the memory, by tunneling through the insulating film beneath the floating gate electrode. The method also calls for the formation of MISFETs associated with peripheral circuitry of the memory.

Method of manufacturing a semiconductor IC device having single

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines. The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

SRAM having load transistor formed above driver transistor

Semiconductor integrated circuit device and process for fabricating the

Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

Process for fabricating a semiconductor integrated circuit device

A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

Growing community of inventors

Hinode-machi, Japan

Satoshi Meguro