The Procter Gamble Company

Murata Manufacturing Co., Ltd.

Nintendo Co., Ltd.

Satoshi Matsumura

Nobuyuki Kitamura

Motoki Tamura

Yuji Shintomi

Shinsuke Nomura

Kazuhiro Nakamuta

Shota Ishihara

Satoru Matsuyama

Toshiki Matsumura

Masanori Iijima

Jamie Trafford Stone

Yoshihiro Taki

Tomoko Nanno

Masafumi Sakashita

A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal.

Data communication device and data communication module

A digital output monitor circuit includes a first digital circuit that performs mutual conversion between serial data and parallel data, a second digital circuit that decodes data output from the first digital circuit and generates a control signal for an analog circuit, and a third digital circuit that converts at least the control signal for an analog circuit into digital data. The first digital circuit converts the data output from the third digital circuit into serial data and outputs as an output data signal.

Digital output monitor circuit and high frequency front-end circuit

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

Counter readout circuit

An interface circuit and a communication apparatus that can reduce the circuit scale and power consumption are provided. An interface circuit includes a plurality of communication devices, an analog-to-digital (AD) conversion circuit that converts an analog signal to digital data, and a control circuit that reads the digital data in response to read-request signals received from the plurality of communication devices.

Interface circuit and communication apparatus

A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.

Power amplifier module

Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.

Data transfer device and wireless communication circuit

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

Growing community of inventors

Kyoto, Japan

Satoshi Matsumura