Sanyo Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sharp Corporation

Satoshi Matsumoto

Souichi Miyata

Kenji Shima

Shinji Komori

Hiroki Miura

Hiroaki Terada

Hajime Asano

Masahisa Shimizu

Katsuhiko Asada

Hiroaki Nishikawa

Daisuke Azuma

Hikaru Katsuki

Toshiya Okamoto

Masayuki Shimizu

Kazuharu Nishitani

Masao Takiguchi

Niroaki Nishikawa

Taiji Imazu

Tetsuo Yamasaki

Manabu Ishihara

Tomonori Isobe

Shin'ichi Yoshida

Takeshi Fukuhara

Futoshi Miyamae

Kouichi Matsumoto

Hiroshi Yoshida

Yuki Takatsu

Eiji Kawabe

Katushiko Asada

There is provided a controlling apparatus for an air conditioner, which comprises: an inverter circuit for feeding as an output a pseudo-sine wave from a switching signal obtained by comparison between a modulated wave and a carrier wave; a refrigeration cycle device which has a compressor driven by the pseudo-sine wave from the inverter circuit so that the modulated wave is adjusted according to a load of an air conditioner; and a correction device for correcting an amplitude of the modulated wave into a smaller one at a predetermined time when a rated voltage of the power source from the inverter circuit is larger than a rated voltage by a first predetermined value, and correcting the modulated wave into a larger one at a predetermined time when a rated voltage of the power source from the inverter circuit is smaller than the rated voltage by a second predetermined value. The predetermined time is elongated as the difference between the aforementioned power source voltage and the rated voltage becomes larger, so that shutdown of the compressor is restricted at the voltage variation of the power source.

Apparatus for controlling an air conditioner

An inexpensive control system for a multiple-type air conditioner makes it possible to automatically and independently detect frosting and conduct defrosting control in an outdoor unit during a reverse cycle heating operation in a two-compressor, multiple-type air conditioner which has an outdoor unit equipped only with a simple ON/OFF control function and which is not provided with a signal conductor for transmitting the information on the state of an outdoor unit to an indoor unit. In this case, the operation of the outdoor unit can be determined, monitored, and controlled from the indoor unit side so as to enable proper action to be taken. The control system is provided with means for independently controlling the operation of the outdoor unit and means for determining the operation of the outdoor unit from the indoor unit side according to the state of an indoor side heat exchanger and for controlling the operation of the air conditioner.

Control system for multiple-type air conditioner

A defrosting control method wherein an indoor unit determines whether a drop in the temperature gradient of an indoor side heat exchanger has been caused by a heavy load protecting operation or frosting of the outdoor heat exchanger during a reverse cycle heating operation of a two-unit-type air conditioner. The defrosting control is not triggered when the heavy load protecting operation is being carried out, and the defrosting control is started when predetermined conditions are satisfied, including the temperature of the indoor heat exchanger being below a raised predetermined temperature during a heavy load protecting operating.

Defrosting control method for air conditioner

A control device of an air conditioner comprises a first controller which is installed in a room to be air-conditioned and which generates the signals for controlling an air conditioner. A second controller, which is installed in a different room from the room to be air-conditioned also generates signals for controlling the air conditioner. A main controller which receives the signals from the first controller via a first interface and receives the signals from the second controller via second interface, controls the air conditioner in accordance with the two types of signals. The first controller is designed such that once the signal for starting the air conditioning operation of the air conditioner has been sent to the first interface, the first controller sends the signal for running the air conditioner in a predetermined cycle to the first interface until the first controller transmits to the first interface the signal for stopping the operation of the air conditioner. The main controller is designed to invalidate the signal for running the air conditioner, which is received through the first interface, once it has received the signal for stopping the air conditioning operation of the air conditioner from the second controller through the second interface.

Dual control device of an air conditioner

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Associative storage for data packets including asynchronous,

In order to obtain an output circuit having pulldown resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an OR gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pulldown transistor (Q.sub.1) are connected to a second input end and an output end of the OR gate (G5) respectively. The pulldown transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.SS) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a high logical level, the pulldown transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to lower the potential of the input end of the inverter (11).

Pulldown resistance control input circuit and output circuit

In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).

Pullup resistance control input circuit and output circuit

A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Parallel processing development system with debugging device includes

A data transmission apparatus including an input-side data transmission path having a first-stage data transmission path, a second-stage data transmission path and a plurality of output-side data transfer paths is provided. When data, which include an identifier for designating the output-side data, transfer path are carried on the input-side transmission path, a comparison/decision logic unit compares the identifier in the data to be transferred and a data destination bit separately supplied thereto. The compared results are supplied to a branch control which produces a select bit for specifying one of the plurality of the outgoing data transfer paths. The incoming data together with a sending signal are passed through the first and second stage input-side data transmission paths toward the plurality of the output-side data transfer paths. The data are then transferred through one particular output-side data transfer path selected by the application of a select bit supplied thereto.

Data transmission apparatus for autonomously and selectively

A data flow type information processor includes a program storing portion, a paired data detecting portion, an operation processing portion, an internal data buffer, and an external data memory. A data packet processed in the program storing portion, the paired data detecting portion and the operation processing portion is transferred to the internal data buffer. On the other hand, a data packet outputted from the external data memory is transferred to another information processor through a merge portion, a branch portion, another merge portion and another branch portion. Thus, internal processing through the internal data buffer and processing from the external data memory to the exterior are not merged.

Data flow type information processors where data packets pass through

A first-in first-out type memory is used as a buffer for data transfer between asynchronous systems. This buffer memory has a minimum delay elastic buffer function in which the number of data storage stages is changed according to the data transfer situation in an output portion of the memory. The data storage memory includes a folded type data transmission path with a going path and a returning path respectively provided with data storage devices of the same number, bypassing paths for coupling corresponding data storage devices in the going path and the returning path, and a valid data detector provided corresponding to each of the bypassing paths for detecting the presence or absence of valid data in a data storage device closer to an input/output portion than a corresponding bypassing path and making the bypassing path enabled or disabled according to the result of the detection.

FIFO buffer with folded data transmission path permitting selective

Two input-side data transmission paths are provided in parallel with each other, and a competition detecting part detects the time difference between times of arrival of transmission signals supplied to the respective data transmission paths for stopping the data arriving with a delay on the data transmission path therefor if the time difference is within a constant range. Thereby, the time difference is rendered to be outside of the constant range. A word number counting part counts the word numbers of the data transmitted to the data transmission paths, and an arbitration control part supplies transmission authorizing signals to the respective input-side data transmission paths for transmitting the data of the counted word numbers to an output-side data transmission path. The two input-side data transmission paths are provided with buffer mechanisms for changing the amounts of data delay in response to the degree of data occupancy.

Data transmission unit

A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.

Data transmission apparatus

By providing a tag data renewing unit in a data flow-computer, the 'delay' function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.

Information processing apparatus for a data flow computer

A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

Growing community of inventors

Nara, Japan

Satoshi Matsumoto