Fujitsu Corporation

Fujitsu Semiconductor Limited

Satoshi Matsui

Seiji Suetake

Yukihiro Ozawa

A power supply voltage regulator circuit including a power supply circuit which switches to a first through a fourth state; the first state being the state wherein voltage is supplied to neither a normal circuit nor a backup system circuit based on the combination of logic for the normal circuit power control signal, the second state being the state wherein a primary power supply voltage is supplied to the normal circuit and a secondary power supply voltage is supplied to the backup system circuit, the third state being the state wherein voltage is not supplied to the normal circuit and the secondary power supply voltage is supplied to the backup system circuit, the fourth state being the state wherein the primary power supply voltage is supplied to both the normal circuit and the backup system circuit.

Power supply voltage regulator circuit and microcomputer

When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at the write access to the upper side, and writes the data of the data bus to the lower side and writes the data of the write buffer to the upper side at the write access to the lower side. At the read access to the lower side of the counter, the timer reads the data of the lower side for output to the data bus and reads the data of the upper side for storage in the read buffer. At the read access to the upper side, it outputs data of the read buffer to the data bus.

Semiconductor integrated circuit

A PWM circuit includes a counter, a cycle register, a cycle detector, a pulse width register, a pulse width detector, an additional pulse width register, a voltage generator, a selector, and a voltage controller. The voltage controller controls the selector so as to add a first additional pulse at a first voltage to the end of a pulse width, based on a cycle detection signal outputted by the cycle detector, a pulse width detection signal outputted by the pulse width detector, and a set value indicating the first voltage of the first additional pulse outputted by the additional pulse register, thereby deciding a voltage outputted from the PWM circuit and a period in which the voltage is output.

Pulse width modulation circuit

A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.

Semiconductor integrated circuit having changeable bus width of external data signal

A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.

Clock shift circuit for gradual frequency change

A pulse width measuring device is disclosed that calculates the pulse width of a signal to be measured, based on a count value and a count clock signal. In the pulse width measuring device, the counter circuit has a plurality of bits that are divided into an exponent and a significand. The control unit of the pulse width measuring device includes: an exponent storing unit that stores an exponent setting value that represents the number of bits of the exponent of the counter circuit; and a decoder unit that generates a count value setting signal for rewriting the count value of the counter circuit, based on the exponent setting value stored in the exponent storing unit, when the count value overflows in the counter circuit, the decoder unit then outputting the count value setting signal to the counter circuit.

Pulse width measuring device with automatic range setting function

A direct memory access controller includes: one request signal input terminal for inputting a request signal while at least one of a plurality of request devices is outputting the request signal; one acknowledge signal output terminal for outputting an acknowledge signal to the plurality of request devices; and a control circuit. The control circuit outputs the acknowledge signal from the acknowledge signal output terminal and thereafter controls a data transfer based on the request signal from one of the plurality of request devices in response to a timing when the request signal inputted from the request signal input terminal changes in level.

Direct memory access controller, direct memory access device, and request device

A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Apparatus for changing pulse width modulation at desired timing

A product-sum device has a data register and a coefficient register and calculates the sum of products of the outputs of the data register and coefficient register. The data register has register elements that successively shift presently held data whenever new data is supplied to the data register. The coefficient register has register elements corresponding to the register elements. The product-sum device carries out a filtering operation at high speed.

Product-sum device suitable for IIR and FIR operations

An improvement of the present invention relates to a data length deciding unit of an information processing apparatus using instructions having different data length. The information processing apparatus has a compact ROM for storing microprograms. The information processing apparatus comprises a data length specifying unit for specifying either directly specified data length information or indirectly specified data length information, a storing unit for storing data length information related to a process not contained in the microprograms, a controlling unit for controlling the storing unit, and a selecting unit for selecting one of the outputs of the data length specifying unit and storing unit, and outputting the selected one.

Apparatus for handling differing data length instructions using either

An information processing system includes an instruction decoder part for decoding an external instruction signal and for outputting a control signal for executing an instruction based on a decoded result, and an operation part for carrying out an operation based on the control signal and for outputting an operation result. The operation part includes an operation unit which carries out an arithmetic logic operation and outputs the operation result, a flag register for holding states related to the operation result based on the control signal, and a buffer for successively holding predetermined states related to the operation result. The operation unit carries out the arithmetic logic operation by selectively reading the states held in the flag register and the buffer.

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Kawasaki, Japan

Satoshi Matsui