Renesas Electronics Corporation

Nec Electronics Corporation

Satoshi Matsui

Masaya Kawano

Nobuaki Takahashi

Masahiro Komuro

Koji Soejima

Shinji Watanabe

Yoichiro Kurita

Akira Matsumoto

Hirokazu Honda

Tsuyoshi Eda

Yoshitaka Kyougoku

In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance rfrom the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance rin the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

Semiconductor device

A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.

Method of stacking semiconductor chips including forming an interconnect member and a through electrode

A semiconductor deviceis provided with a multiplex through plugthat fills an opening extending through the silicon substrate. The multiplex through plugscomprises a column-shaped and solid first through electrode, a first insulating filmthat covers the cylindrical face of the first through electrode, a second through electrodethat covers the cylindrical face of the first insulating filmand a second insulating filmthat covers the cylindrical face of the second through electrode, and these have a common central axis. The upper cross sections of the first insulating film, the second through electrodeand the second insulating filmare annular-shaped.

Semiconductor device providing a first electrical conductor and a second electrical conductor in one through hole and method for manufacturing the same

A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.

Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.

Semiconductor device including through electrode and method of manufacturing the same

A semiconductor deviceis provided with a multiplex through plugthat fills an opening extending through the silicon substrateThe multiplex through plugscomprises a column-shaped and solid first through electrodea first insulating filmthat covers the cylindrical face of the first through electrodea second through electrodethat covers the cylindrical face of the first insulating filmand a second insulating filmthat covers the cylindrical face of the second through electrodeand these have a common central axis. The upper cross sections of the first insulating filmthe second through electrodeand the second insulating filmare annular-shaped.

A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode.

Semiconductor device and semiconductor module employing thereof

The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.

Chip and multi-chip semiconductor device using the chip, and method for manufacturing same

The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holesextending through the silicon substrateis provided. An insulating filmis buried within the through hole. A plurality of columnar through plugsare provided in the insulating film

Semiconductor device having a through electrode, semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode

The semiconductor device includes a silicon interposer made of a semiconductor and a first semiconductor chip mounted on one surface of the silicon interposer. The semiconductor device is provided with a through electrode penetrating the silicon interposer and having a side surface insulated from the silicon interposer; and a wiring connecting one end of the through electrode and the silicon interposer. The through electrode is connected to a power supply wiring or a GND wiring provided on the first semiconductor chip.

Semiconductor device and method for producing the same

Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode

The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substratehas bumpsarranged on one surface thereof, and has a first chipmounted on the other surface thereof. A second chipis bonded to the first chipthrough bumpswhile offsetting the second chipto the first chipin parallel. In the bonded state of the first chipand the second chipa part of the first chipand a part of the second chipare overlapped without aligning the centers of the both. The center of gravity of the second chipfalls inside a region surrounded by the outermost bumps between the first chipand the second chip

Growing community of inventors

Kanagawa, Japan

Satoshi Matsui