Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Satoshi Kowatari

Hiroaki Iwashita

Tsuneo Nakata

Fumiyasu Hirose

Takako Shindo

Yoshiro Nakamura

A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay generator inserter produces a delay-insertable version of the circuit by embedding a delay generator into each found CDC path. When activated, those delay generators give a signal delay to the corresponding CDC paths. A simulator simulates the behavior of the delay-insertable circuit by using a specified simulation pattern while deactivating the embedded delay generators. A delay pattern generator creates a delay pattern from simulation results, which activates or deactivates delay generators individually so as to produce signal delays that could affect output signals of the circuit. A verifier verifies the circuit by applying the delay pattern to each delay generator in the circuit.

Apparatus, method, and program for verifying logic circuit operating with multiple clock signals

A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.

Method and apparatus for supporting verification, and computer product

A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit description information on the object; a specifying unit that specifies at least two registers in one clock domain that output data to an adjacent clock domain; and a detecting unit that detects, based on the logical circuit description information and specified registers, a re-convergence register in the adjacent clock domain that achieves convergence.

Apparatus and method for verification support, and computer product

First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.

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Kawasaki, Japan

Satoshi Kowatari