Elpida Memory, Inc.

Satoshi Katagiri

Yukio Fuji

Kenji Mae

Yasuko Tonomura

A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite&#x3e;VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device.

Phase change memory device

In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.

Semiconductor memory device having DRAM-compatible addressing mode and data processing system including same

A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA) and (SA) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA) perform a converting operation during an amplifying operation performed by the sense amplifier (SA). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.

Semiconductor memory device and method with two sense amplifiers

A semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory elements arranged at intersecting points between the word lines and the bit lines, respectively, a row selector selectively activating the word lines, a plurality of write drivers provided to correspond to the bit lines, and supplying a write current to the corresponding bit lines, respectively, a plurality of write control circuits controlling operations performed by the corresponding write drivers, respectively, and a column selector selecting the write control circuits. The column selector sequentially selects a predetermined write control circuit per one clock in a state of activating a predetermined word line, and the selected write control circuit activates one corresponding write driver over a period of one clock or more.

Semiconductor memory device and write control method thereof

A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written.

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Tokyo, Japan

Satoshi Katagiri